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MPC604EC/D データシート(PDF) 6 Page - NXP Semiconductors |
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MPC604EC/D データシート(HTML) 6 Page - NXP Semiconductors |
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6 / 32 page  6 604 Hardware Specifications Preliminary/Subject to Change without Notice Figure 3 provides the timing diagram for the fast-L2 mode select input. Figure 3. Fast-L2 Mode Select Input Timing Diagram 1.3.3 Output AC Specifications Table 7 provides the output AC timing specifications for the 604 (shown in Figure 4). Table 7. PowerPC 604 Microprocessor Output AC Timing Specifications Vdd = 3.3 ± 5% V dc, GND = 0 V dc, CL = 50 pF, 0 ≤ Tj ≤ 105 °C Num Characteristic 100 MHz 120 MHz 133 MHz Unit Notes Min Max Min Max Min Max 12 SYSCLK to output driven (output enable time) 0.75 — 0.75 — 0.75 — ns 1 13a SYSCLK to TS, XATS, ARTRY, SHD, ABB, and DBB output valid (for 5.5 V to 0.8 V) — 8.5 — 7.5 — 7.0 ns 2 13b SYSCLK to TS, XATS, ARTRY, SHD, ABB, and DBB output valid (for 3.6 V to 0.8 V) — 7.5 — 6.5 — 6.0 ns 14a SYSCLK to all other signals output valid (for 5.5 V to 0.8 V) — 8.5 — 7.5 — 7.0 ns 2 14b SYSCLK to all other signals output valid (for 3.6 V to 0.8 V) — 7.5 — 6.5 — 6.0 ns 15 SYSCLK to output invalid (output hold) 1.0 — 1.0 — 1.0 — ns 16 SYSCLK to output high impedance (all signals except ARTRY, SHD, ABB, DBB, TS, and XATS) — 7.0 — 6.5 — 6.0 ns 17 SYSCLK to output high impedance TS, XATS — 7.0 — 6.5 — 6.0 ns 18 SYSCLK to ABB and DBB high impedance after precharge — 1.0* tsysclk — 1.0* tsysclk — 1.0* tsysclk ns 3 19 SYSCLK to ARTRY and SHD high impedance before precharge — 7.0 — 6.5 — 6.0 ns FAST-L2 MODE PIN HRESET 11 VM VM = Midpoint Voltage (1.4V) 10 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com AR CH IVE D B Y F RE ES CA LE SE MI CO ND UC TO R, INC . |
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