604 Hardware Specifications

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Preliminary/Subject to Change without Notice

1.3.2 Input AC Specifications

Table 6 provides the input AC timing specifications for the 604 as defined in Figure 2.

Figure 2 provides the input timing diagram for the 604.

Figure 2. PowerPC 604 Microprocessor Input Timing Diagram

Table 6. PowerPC 604 Microprocessor Input AC Timing Specifications

Vdd = 3.3

± 5% V dc, GND = 0 V dc, 0 ≤ T

j ≤ 105 °C

Num

Characteristic

100 MHz

120 MHz

133 MHz

Unit

Notes

Min

Max

Min

Max

Min

Max

7ARTRY, SHD, ABB, TS, XATS,

AACK,BG, DRTRY, TA, DBG, DBB, TEA,

DBDIS, and DBWO valid to SYSCLK

(setup)

5.5

—

5.0

—

5.0

ns

8

All other inputs valid to SYSCLK (setup)

5.5

—

4.0

—

4.0

—

ns

1

9

SYSCLK to all inputs invalid (hold)

0

—

0

—

0

—

ns

1

10

Mode select input valid to HRESET (input

setup for DRTRY)

8 *

tsysclk

—

8 *

tsysclk

—

8 *

tsysclk

—

ns

2,3,4,5

11

HRESET to mode select input invalid

(input hold for DRTRY)

0

—

0

—

0

—

ns

2,3,4,5

Notes:

1. All other input signals include the following signals—all inputs except ARTRY, SHD, ABB, TS, XATS,

AACK, BG, DRTRY, TA, DBG, DBB, DBWO, DBDIS, TEA, and JTAG inputs.

2. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3).

3. tsysclk is the period of the external clock (SYSCLK) in nanoseconds.

4. These values are guaranteed by design, and are not tested.

5. Note this is for configuration of the fast-L2 mode. The DRTRY signal must be held negated during fast-L2

mode.

VM

SYSCLK

ALL INPUTS

VM = Midpoint Voltage (1.4V)

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9

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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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