AD9397

Rev. 0 | Page 8 of 28

Pin Type

Pin No.

Mnemonic

Function

Value

POWER SUPPLY

80, 76, 72, 67,

45, 33

Analog Power Supply and DVI Terminators

3.3 V

100, 90, 10

Output Power Supply

1.8 V to 3.3 V

59, 56, 54

PLL Power Supply

1.8 V

48, 32, 30

Digital Logic Power Supply

1.8 V

GND

Ground

0 V

CONTROL

83

SDA

Serial Port Data I/O

3.3 V CMOS

82

SCL

Serial Port Data Clock

3.3 V CMOS

HDCP

49

DDCSCL

HDCP Slave Serial Port Data Clock

3.3 V CMOS

50

DDCSDA

HDCP Slave Serial Port Data I/O

3.3 V CMOS

51

MCL

HDCP Master Serial Port Data Clock

3.3 V CMOS

52

MDA

HDCP Master Serial Port Data I/O

3.3 V CMOS

DATA ENABLE

88

DE

Data Enable

3.3 V CMOS

RTERM

46

RTERM

Sets Internal Termination Resistance

500 Ω

Table 6. Pin Function Descriptions

Pin

Description

INPUTS

Rx0+

Digital Input Channel 0 True.

Rx0−

Digital Input Channel 0 Complement.

Rx1+

Digital Input Channel 1 True.

Rx1−

Digital Input Channel 1 Complement.

Rx2+

Digital Input Channel 2 True.

Rx2−

Digital input Channel 2 Complement.

These six pins receive three pairs of transition minimized differential signaling (TMDS ) pixel data

(at 10× the pixel rate) from a digital graphics transmitter.

RxC+

Digital Data Clock True.

RxC−

Digital Data Clock Complement.

This clock pair receives a TMDS clock at 1× pixel data rate.

PWRDN

Power-Down Control/Three-State Control.

The function of this pin is programmable via Register 0x26 [2:1].

RTERM

RTERM is the termination resistor used to drive the AD9397 internally to a precise 50 Ω termination for

TMDS lines. This should be a 500 Ω 1% tolerance resistor.

OUTPUTS

HSOUT

Horizontal Sync Output.

A reconstructed and phase-aligned version of the HSYNC input. Both the polarity and duration of this

output can be programmed via serial bus registers. By maintaining alignment with DATACK and Data,

data timing with respect to horizontal sync can always be determined.

VSOUT

Vertical Sync Output.

The separated VSYNC from a composite signal or a direct pass through of the VSYNC signal. The polarity

of this output can be controlled via the serial bus bit (Register 0x24 [6]).

FIELD

Odd/Even Field Bit for Interlaced Video. This output identifies whether the current field (in an interlaced

signal) is odd or even. The polarity of this signal is programmable via Register 0x24[4].

DE

Data Enable that defines valid video. Can be received in the signal or generated by the AD9397.

CTL(3-0)

Control 3, Control 2, Control 1, and Control 0 are output from the DVI stream. Refer to the DVI 1.0

specification for explanation.

SERIAL PORT

SDA

SCL

Serial Port Data Clock for Programming AD9397 Registers.

DDCSDA

DDCSCL

Serial Port Data Clock for HDCP Communications to Transmitter.

MDA

MCL

Serial Port Data Clock to EEPROM with HDCP Keys.