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AD9397/PCB データシート(PDF) 14 Page - Analog Devices |
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AD9397/PCB データシート(HTML) 14 Page - Analog Devices |
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14 / 28 page  AD9397 Rev. 0 | Page 14 of 28 Hex Address Read/Write or Read Only Bits Default Value Register Name Description [4] **1**** ield Output Polarity utput field polarity. * F O 0 = active low out. 1 = active high out. [0] ******0 utput CLK Invert out. * O 0 = Don’t invert clock 1 = Invert clock out. 0x25 Read/Write :6] 1****** utput CLK Select use on output pin. 1× CLK is divided [7 0 O Selects which clock to down from TMDS clock input when pixel repetition is in use. 00 = ½× CLK. 01 = 1× CLK. 10 = 2× CLK. 11 = 90° phase 1× CLK. [5:4] *11**** utput Drive f the outputs. * O Strength Sets the drive strength o 00 = lowest, 11 = highest. [3:2] ***00** utput Mode comes out on. * O Selects which pins the data 00 = 4:4:4 mode (normal). 01 = 4:2:2 + DDR 4:2:2 on blue. 10 = DDR 4:4:4 + DDR 4:2:2 on blue. [1] *****1* rimary Output * P Enable Enables primary output. [0] *******0 ry Output Enables secondary output (DDR 4:2:2 in Output Mode 1 and Seconda Enable Mode 2). 0x26 Read/Write [7] 0******* ee-State e the outputs. Output Thr Three-stat [5] **0***** SPDIF Three-State Three-state the SPDIF output. [4] ***0**** I2S Three-State Three-state the I2S output and the MCLK out. [3] ****1*** Power-Down Pin Polarity Sets polarity of power-down pin. 0 = active low. 1 = active high. [2:1] ****00* ower-Down Pin wer-down pin. * P Function Selects the function of the po 00 = power-down. 01 = power-down and three-state SOG. 10 = three-state outputs only. 11 = three-state outputs and SOG. [0] ******0 ower-Down * P 0 = normal. 1 = power-down. 0x27 Read/Write ] ******* uto Power-Down w power state. [7 1 A Enable 0 = disable auto lo 1 = enable auto low power state. [6] 0****** DCP A0 HDCP I2C. Set to 1 only for a * H Sets the LSB of the address of the second receiver in a dual-link configuration. 0 = use internally generated MCLK. 1 = use external MCLK input. [5] *0***** CLK External must be locked to the video clock * M Enable If an external MCLK is used, it according to the CTS and N available in the I2C. Any mismatch between the internal MCLK and the input MCLK results in dropped or repeated audio samples. [4] ***0**** BT656 EN into the video output Enables EAV/SAV codes to be inserted data. [3] ****0*** Force DE Generation use of the internal DE generator in DVI mode. Allows [2:0] n Field 0 *****000 Interlace Offset Sets the difference (in HSYNCs) in field length betwee and Field 1. |
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