AD9882ASLASHPCB datasheet(28/40 Pages) AD

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AD9882A

Rev. 0 | Page 28 of 40

0x0F 1

AIS Active Interface Select

This bit is used under two conditions. It is used to select the

active interface when the override bit is set (Register 0x0F,

Bit 2). Alternatively, it is used to determine the active interface

when not overriding but both interfaces are detected.

Table 16. Active Interface Select Settings

AIS

Result

Analog interface

Digital interface

The default for this register is 0.

0x10 7

Hsync Input Polarity Override

This register is used to override the internal circuitry that

determines the polarity of the Hsync signal going into the PLL.

Table 17. Hsync Input Polarity Override Settings

Override Bit

Result

Hsync polarity determined by chip.

Hsync polarity determined by Register 0x10,

Bit 6.

The default for Hsync polarity override is 0. (Polarity

determined by chip.)

0x10 6

HSPOL Hsync Input Polarity

A bit that must be set to indicate the polarity of the Hsync

signal that is applied to the PLL Hsync input.

Table 18. Hsync Input Polarity Settings

HSPOL

Function

Active low

Active high

Active low means the leading edge of the Hsync pulse is

negative-going. All PLL timing is based on the leading edge

of Hsync, which is the falling edge. The rising edge is used to

time the internal clamping.

Active high means the leading edge of the Hsync pulse is

positive-going. This means that PLL timing is based on the

leading edge of Hsync, which is now the rising edge.

The device operates if this bit is set incorrectly, but the

internally generated clamp position, as established by clamp

placement (Register 0x05), is not placed as expected, which

might generate clamping errors.

The power-up default value for HSPOL is 1.

0x10 5

Hsync Output Polarity

This bit determines the polarity of the Hsync output and the

SOG output. Table 19 shows the effect of this option. Sync

indicates the logic state of the sync pulse.

Table 19. Hsync Output Polarity Settings

Setting

SYNC

Logic 1 (positive polarity)

Logic 0 (negative polarity)

The default setting for this register is 0.

0x10 4

Active Hsync Override

This bit is used to override the automatic Hsync selection. To

override, set this bit to Logic 1. When overriding, the active

Hsync is set via Bit 3 in this register.

Table 20. Active Hsync Override Settings

Override

Result

Autodetermines the active Hsync.

Override; Bit 3 determines the active Hsync.

The default for this register is 0.

0x10 3

Active Hsync Select

This bit is used under two conditions. It is used to select the

active Hsync when the override bit is set (Bit 4). Alternatively, it

is used to determine the active Hsync when not overriding, but

both Hsyncs are detected.

Table 21. Active Hsync Select Settings

Select

Result

Hsync input

Sync-on-green input

The default for this register is 0.

0x10 2

Vsync Output Polarity

This bit determines the polarity of the Vsync output. Table 22

shows the effect of this option. SYNC indicates the logic state of

the sync pulse.

Table 22. Vsync Output Polarity Settings

Setting

SYNC

Not inverted

Inverted

The default setting for this register is 0.

0x10 1

Active Vsync Override

This bit is used to override the automatic Vsync selection. To

override, set this bit to Logic 1. When overriding, the active

interface is set via Bit 0 in this register.

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