AD9882ASLASHPCB datasheet(20/40 Pages) AD

20 / 40 page

AD9882A

Rev. 0 | Page 20 of 40

MCL—HDCP Master Serial Port Data Clock

Connects to the EEPROM for reading the encrypted HDCP

keys.

MDA—HDCP Master Serial Port Data I/O

Connects to the EEPROM for reading the encrypted HDCP

keys.

CTL—Digital Control Outputs

These pins output the control signals for the red and green

channels. CTL0 and CTL1 correspond to the red channel’s

input, while CTL2 and CTL3 correspond to the green channel’s

input.

Power Supply

VD—Main Power Supply

It should be as quiet as possible.

PVD—PLL Power Supply

It should be as quiet as possible.

VDD—Outputs Power Supply

The power for the data and clock outputs. It can run at 3.3 V

or 2.5 V.

GND—Ground

The ground return for all circuitry on the device. It is recom-

mended that the application circuit board have a single, solid

ground plane.

CAPTURING THE ENCODED DATA

The first step in recovering the encoded data is to capture the

raw data. To accomplish this, the AD9882A employs a high

speed phase-locked loop (PLL) to generate clocks capable of

over sampling the data at the correct frequency. The data

capture circuitry continuously monitors the incoming data

during horizontal and vertical blanking times (when DE is low)

and selects the best sampling phase for each data channel

independently. The phase information is stored and used until

the next blanking period (one video line).

DATA FRAMES

The digital interface data is captured in groups of 10 bits each,

which are called data frames. During the active data period,

each frame is made up of the nine encoded video data bits and

one dc-balancing bit. The data capture block receives this data

serially but outputs each frame in parallel 10-bit words.

SPECIAL CHARACTERS

During periods of horizontal or vertical blanking time (when

DE is low), the digital transmitter transmits special characters.

The AD9882A receives these characters and uses them to set

the video frame boundaries and the phase recovery loop for

each channel. There are four special characters that can be

received. They are used to identify the top, bottom, left side, and

right side of each video frame. The data receiver can

differentiate these special characters from active data because

the special characters have a different number of transitions per

data frame.

CHANNEL RESYNCHRONIZATION

The purpose of the channel resynchronization block is to

resynchronize the three data channels to a single internal data

clock. Coming into this block, all three data channels can be on

different phases of the 3× oversampling PLL clock (0°, 120°, and

240°). This block can resynchronize the channels from a worst-

case skew of one full input period (8.93 ns at 112 MHz).

DATA DECODER

The data decoder receives frames of data and sync signals from

the data capture block (in 10-bit parallel words) and decodes

them into groups of eight RGB bits, two control bits, and a data

enable bit (DE).

HDCP

The AD9882A contains all the circuitry necessary for

decryption of a high bandwidth digital content protection

encoded DVI video stream. A typical HDCP implementation

is shown in Figure 12. Several features of the AD9882A make

this possible and add functionality to ease the implementation

of HDCP.

The basic components of HDCP are included in the AD9882A.

A slave serial bus connects to the DDC clock and DDC data

pins on the DVI connector to allow the HDCP-enabled

DVI transmitter to coordinate the HDCP algorithm with

the AD9882A. A second serial port (MDA/MCL) allows the

AD9882A to read the HDCP keys and key selection vector

(KSV) stored in an external serial EEPROM. When

transmitting encrypted video, the DVI transmitter enables

HDCP through the DDC port. The AD9882A then decodes the

DVI stream using information provided by the transmitter,

HDCP keys, and KSV.

The AD9882A allows the MDA and MCL pins to be three-

stated using the MDA/MCL three-state bit (Register 0x1B, Bit

7) in the configuration registers. The three-state feature allows

the EEPROM to be programmed in-circuit. The MDA/MCL

port must be three-stated before attempting to program the

EEPROM using an external master. The keys will be stored in

an I2C® compatible 3.3 V serial EEPROM of at least 512 bytes in

size. The EEPROM should have a device address of 0xA0.

Proprietary software licensed from Analog Devices encrypts the

keys and creates properly formatted EEPROM images for use in

a production environment. Encrypting the keys helps maintain

AD9882A/PCB データシート(PDF) 20 Page - Analog Devices

AD9882A/PCB データシート(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

データシートダウンロード