AD9882ASLASHPCB datasheet(30/40 Pages) AD

30 / 40 page

AD9882A

Rev. 0 | Page 30 of 40

0x11 1 Coast Input Polarity

This bit indicates the polarity of the coast signal that is applied

to the PLL coast input.

This register can be used only when coast is disabled and

Table 31. Coast Input Polarity Settings

CSTPOL

Function

Active low

Active high

The power-up default value is CSTPOL = 1.

0x12 7–0

Precoast

This register allows the coast signal to be applied prior to the

Vsync signal. This is necessary in cases where pre-equalization

pulses are present. This register defines the number of edges

that are filtered before Vsync on a composite sync.

The default is 0.

0x13 7–0 Postcoast

This register allows the coast signal to be applied following the

Vsync signal. This is necessary in cases where postequalization

pulses are present. The step size for this control is one Hsync

period. This register defines the number of edges that are

filtered after Vsync on a composite sync.

The default is 0.

0x14 7–6 Output Drive

These two bits select the drive strength for the high speed

digital outputs (all data output and clock output pins). Higher

drive strength results in faster rise/fall times, and in general

makes it easier to capture data. Lower drive strength results in

slower rise/fall times and helps reduce EMI and digitally

generated power supply noise.

Table 32. Output Drive Strength Settings

Bit 7

Bit 6

Result

High drive strength

Medium drive strength

Low drive strength

The default for this register is 11, high drive strength. This

option works on both the analog and digital interfaces.

0x14 5

Programmable Analog Bandwidth

These bits select the analog bandwidth.

Table 33. Analog Bandwidth Control

Bit 5

Analog Bandwidth

10 MHz

300 MHz

0x14 4

Clk Inv Data Output Clock Invert

A control bit for the inversion of the output data clock (Pin 85).

This function works only for the digital interface. When not

inverted, data is output on the falling edge of the data clock. See

the Timing Diagrams sections, Figure 14 and Figure 15, to see

how this affects timing.

Table 34. Clock Output Invert Settings

Clk Inv

Function

Not inverted

Inverted

The default for this register is 0 (not inverted).

0x14 3

PDO Power-Down Outputs

This bit is used to put the outputs in a high impedance mode.

This applies to the 24 data output pins, HSOUT, VSOUT, and

DE pins.

Table 35. Power-Down Output Settings

PDO

Function

Normal operation

Three-state

The default for this register is 0. (This option works on both the

analog and digital interfaces.)

0x14 2

HDCP Address

This bit is used to set the HDCP slave port address.

Table 36. HDCP Address Settings

Address Bit

Result

0 for HDCP Slave Port

1 for HDCP Slave Port

The default for this register is 0.

0x14 1

PWRDN

This bit is used to control chip power-down. See the Power

Management section for details about which blocks are actually

powered down.

Table 37. Power-Down Settings

Select

Result

Power-down

Normal operation

The default for this register is 1.

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