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AD9882A/PCB データシート(PDF) 16 Page - Analog Devices |
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AD9882A/PCB データシート(HTML) 16 Page - Analog Devices |
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16 / 40 page  AD9882A Rev. 0 | Page 16 of 40 Four programmable registers are provided to optimize the performance of the PLL. These registers are 1. The 12-bit divisor register (Registers 0x01 and 0x02). The input Hsync frequencies range from 15 kHz to 110 kHz. The PLL multiplies the frequency of the Hsync signal, producing pixel clock frequencies in the range of 12 MHz to 140 MHz. The divisor register controls the exact multiplication factor. This register can be set to any value between 221 and 4095. The divide ratio that is actually used is the programmed divide ratio plus one. 2. The 2-bit VCO range register (Register 0x03, Bits 6 and 7). To improve the noise performance of the AD9882A, the VCO operating frequency range is divided into three overlapping regions. The VCO range register sets this operating range. The frequency ranges for the lowest and highest regions are shown in Table 8. 3. The 3-bit charge pump current register (Register 0x03, Bits 3 to 5). This register allows the current that drives the low-pass loop filter to be varied. The possible current values are listed in Table 9. 4. The 5-bit Phase Adjust Register (Register 0x04, Bits 3 to 7). The phase of the generated sampling clock can be shifted to locate an optimum sampling point within a clock cycle. The phase adjust register provides 32 phase-shift steps of 11.25° each. The Hsync signal with an identical phase shift is available through the HSOUT pin. Table 8. VCO Frequency Ranges PV1 PV0 Pixel Clock Range (MHz) 0 0 12–41 0 1 41–82 1 0 82–140 Table 9. Charge Pump Current/Control Bits Ip2 Ip1 Ip0 Current (µA) 0 0 0 50 0 0 1 100 0 1 0 150 0 1 1 250 1 0 0 350 1 0 1 500 1 1 0 750 1 1 1 1500 The coast function allows the PLL to continue to run at the same frequency, in the absence of the incoming Hsync signal or during disturbances in Hsync (such as equalization pulses). This can be used during the vertical sync period, or any other time that the Hsync signal is unavailable. Also, the polarity of the Hsync signal can be set through the Hsync polarity bit (Register 0x10, Bit 6). If not using automatic polarity detection, the Hsync polarity bit should be set to match the polarity of the Hsync input signal. Table 10. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats Standard Refresh Resolution Horizontal Rate (Hz) Frequency (kHz) Pixel Rate (MHz) VCORNGE CURRENT VGA 640 × 480 60 31.500 25.175 00 101 72 37.700 31.500 00 101 75 37.500 31.500 00 101 85 43.300 36.000 00 110 SVGA 800 × 600 56 35.100 36.000 00 101 60 37.900 40.000 00 110 72 48.100 50.000 01 101 75 46.900 49.500 01 101 85 53.700 56.250 01 101 XGA 1024 × 768 60 48.400 65.000 01 101 70 56.500 75.000 01 110 75 60.000 78.750 01 110 80 64.000 85.500 10 101 85 68.300 94.500 10 101 SXGA 1280 × 1024 60 64.000 108.000 10 101 75 80.000 135.000 10 110 TV Modes 480i 60 15.750 13.500 00 001 480p 60 31.470 27.000 00 100 720p 60 45.000 74.500 01 101 1080i 60 33.750 74.500 01 101 |
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