PC7447AMGH1000LB datasheet(25/44 Pages) ATMEL

25 / 44 page

5387B–HIREL–07/05

PC7447A [Preliminary]

9.2

Dynamic Characteristics

This section provides the AC electrical characteristics for the PC7447A. After fabrication, func-

tional parts are sorted by maximum processor core frequency as shown in Section ”Clock AC

Specifications” on page 25 and tested for conformance to the AC specifications for that fre-

quency. The processor core frequency is determined by the bus (SYSCLK) frequency and the

settings of the PLL_CFG[0:4] signals, and can be dynamically modified using dynamic fre-

quency switching (DFS). Parts are sold by maximum processor core frequency; See “Ordering

Information” on page 42. for information on ordering parts. DFS is described in Section

”Dynamic Frequency Switching (DFS)” on page 17.

9.2.1

Clock AC Specifications

Table 8 provides the clock AC timing specifications as defined in Figure 9-1 on page 26 and rep-

resents the tested operating frequencies of the devices. The maximum system bus frequency,

SYSCLK, given in Table 9-2 on page 25 is considered a practical maximum in a typical single-pro-

cessor system. The actual maximum SYSCLK frequency for any application of the PC7447A will

be a function of the AC timings of the PC7447A, the AC timings for the system controller, bus

loading, printed-circuit board topology, trace lengths, and so forth, and may be less than the

value given in Table 9-2 on page 25.

Table 9-2.

Clock AC Timing Specifications (See Table 6-2 on page 10 for Recommended Operating Conditions)

Symbol

Characteristic

Maximum Processor Core Frequency

Unit

Notes

1000 MHz

1267 MHz

1333 MHz

1420 MHz

VDD = 1.3V

VDD = 1.3

MinMax

Min

Max

MinMax

CORE

Processor core

frequency

600

1000

600

1267

600

1333

600

1420

MHz

(1)(8)(9)

VCO

VCO frequency

1200

2000

1200

2533

1200

2667

1200

2840

MHz

(1)(9)

SYSCLK

SYSCLK frequency

167

MHz

(1)(2)(8)

tSYSCLK

SYSCLK cycle time

6.0

(2)

tKR, tKF

SYSCLK rise and fall

time

–

1.0

–

1–1–1

(3)

KHKL/tSYSCLK

SYSCLK duty cycle

measured at OV

DD/2

(4)

SYSCLK jitter(5)(6)

–

150

–

150

–

150

–

150

(5)(6)

Internal PLL relock

time(7)

–

100

–

100

–

100

–

100

µs

(7)

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