PC7447AMGH1000LB datasheet(37/44 Pages) ATMEL

37 / 44 page

5387B–HIREL–07/05

PC7447A [Preliminary]

13.2 PLL Power Supply Filtering

The AV

DD power signal is provided on the PC7447A to provide power to the clock generation

PLL. To ensure stability of the internal clock, the power supplied to the AV

DD input signal should

be filtered of any noise in the 500 KHz to 10 MHz resonant frequency range of the PLL. A circuit

similar to the one shown in Figure 13-1 using surface mount capacitors with minimum effective

series inductance (ESL) is recommended.

The circuit should be placed as close as possible to the AV

DD pin to minimize noise coupled from

nearby circuits. It is often possible to route directly from the capacitors to the AV

DD pin, which is

on the periphery of the 360 HITCE footprint.

Figure 13-1. PLL Power Supply Filter Circuit

13.3 Decoupling Recommendations

Due to the PC7447A dynamic power management feature, large address and data buses, and

high operating frequencies, the PC7447A can generate transient power surges and high fre-

quency noise in its power supply, especially while driving large capacitive loads. This noise must

be prevented from reaching other components in the PC7447A system, and the PC7447A itself

requires a clean, tightly regulated source of power. Therefore, it is recommended that the sys-

tem designer use sufficient decoupling capacitors, typically one capacitor for every 1-2 V

DD pins,

and a similar or lesser amount for the OV

DD pins, placed as close as possible to the power pins

of the PC7447A. It is also recommended that these decoupling capacitors receive their power

from separate V

DD, OVDD, and GND power planes in the PCB, utilizing short traces to minimize

inductance.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic surface mount technology

(SMT) capacitors should be used to minimize lead inductance. Orientations where connections

are made along the length of the part, such as 0204, are preferable but not mandatory. Consis-

tent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A

Handbook of Black Magic (Prentice Hall, 1993) and contrary to previous recommendations for

decoupling Freescale microprocessors, multiple small capacitors of equal value are recom-

mended over using multiple values of capacitance.

In addition, it is recommended that there be several bulk storage capacitors distributed around

the PCB, feeding the V

DD and OVDD planes, to enable quick recharging of the smaller chip

capacitors. These bulk capacitors should have a low equivalent series resistance (ESR) rating to

ensure the quick response time necessary. They should also be connected to the power and

ground planes through two vias to minimize inductance. Suggested bulk capacitors are: 100-330

µF (AVX TPS tantalum or Sanyo OSCON).

13.4 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropri-

ate signal level. Unless otherwise noted, unused active low inputs should be tied to OV

DD, and

unused active high inputs should be connected to GND. All NC (no connect) signals must

remain unconnected.

VDD

Ω

2.2

µF

2.2

µF

GND

AVDD

Low ESL surface mount capacitors

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