WM8772SEDSSLASHV datasheet(54/73 Pages) WOLFSON

54 / 73 page

WM8772EFT – 32 LEAD TQFP

Production Data

PD Rev 4.2 October 2005

2S MODE

In I

2S mode, the MSB of DIN1/2/3 is sampled by the WM8772EFT on the second rising edge of

BCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on

the first falling edge of BCLK following an ADCLRC transition and may be sampled on the rising edge

of BCLK. ADCLRC and DACLRC are low during the left samples and high during the right samples.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN1/2/3/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

1 BCLK

Figure 49 I

2S Mode Timing Diagram

DSP MODE A

In DSP mode A, the MSB of DAC channel 1 left data is sampled by the WM8772EFT on the second

rising edge on DACBCLK following a DACLRC rising edge. DAC channel 1 right and DAC channels 2

and 3 data follow DAC channel 1 left data (Figure 50).

Figure 50 DSP Mode Audio Interface - Mode A Slave, DAC

DACLRC

DACBCLK

DIN1

Input Word Length (IWL)

1/fs

CHANNEL 1

LEFT

n-1

LSB

MSB

n-1

CHANNEL 1

RIGHT

CHANNEL 2

LEFT

n-1

CHANNEL 3

RIGHT

NO VALID DATA

1 BCLK

Figure 51 DSP Mode Audio Interface - Mode A Master, DAC

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