,

IN S

P(PK, MAX)

M

P T

I

= 2

L

+

±

+

±

CBULK

RO

PRI

SEC

NP

NS

n:1

ISNS

GND

CPFC

QSW

GATE

LEB

+

275mV

S

Q

Q

R

170ns

812ms

FAULT

TIMER

LOGIC

&

CONTROL

RSN

LM3447

OCP

,

AUX2

AUX1

A

OUT(OVP)

S

1.75

R

=

R

N

V

1.75

N

æ

ö

ç

÷

ç

÷

ç

÷

-

ç

÷

è

ø

R EC(PK ,MAX)

A

AUX1

- 6

P

V

N

R

=

,

N

200

10

´

LM3447

www.ti.com

SNOSC65 A – APRIL 2012 – REVISED MAY 2012

(11)

Resistor RAUX2 is then selected to set the desired output overvoltage threshold, VOUT(OVP) based on the

secondary to auxiliary turns-ratio

(12)

It is necessary to select the transformer’s secondary to auxiliary turns-ratio (NA/NS) to ensure that VAUX(OVP) is

tripped before VCC(OVP).

CURRENT SENSE AND OVERCURRENT PROTECTION

Figure 26. Current Sense Circuit

The LM3447 provides switch overcurrent and LED short circuit protection by sensing the current through the

switching transistor, QSW via a series connected sense resistor, RSN, as shown in Figure 26. At the beginning of

each switching cycle, the Leading Edge Blanking (LEB) circuit pulls the ISNS input low for approximately 170ns.

This prevents false tripping of the protection circuit due to voltage spikes caused by switch turn on transients.

The cycle-by-cycle current limit is realized by comparing the sensed voltage at ISNS with the internal 275mV

overcurrent protection threshold. When the sense voltage exceeds 275mV, the switch is immediately turned off

for a duration of 812ms, set by the fault timer and the COMP capacitor, CCOMP is discharged. Under fault

conditions, the LM3447 enters a hiccup mode, attempting to restart the circuit after a duration of 812ms. Upon

clearance of the fault, normal operation resumes.

The overcurrent limit is set by selecting the sense resistor, RSN. It is typical to limit the switch current to two times

the maximum peak primary current, IP(PK,MAX), where

(13)

Copyright © 2012, Texas Instruments Incorporated

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