.

GS( PASS)

H OLD

H LD1

H LD2

13.5

V

I

=

(R

+ R

)

-

.

-6

HOLD(TH)

AC VAC(HOLD)

AC

V

= R

I

= 95

10 R

´

VFLT2

1.2V

1V

VFLT1

ENHOLD

IHOLD

1.75V

VREC

VHOLD(TH)

VADET(TH)

t

t

t

t

t

LM3447

www.ti.com

SNOSC65 A – APRIL 2012 – REVISED MAY 2012

HOLD CURRENT CIRCUIT

The LM3447 incorporates an efficient hold current circuit to enhance compatibility with TRIAC based leading

edge dimmers. Holding current from an external dimmer is drawn before the Flyback PFC circuit through the

pass transistor, QPASS and limited by resistors RHLD1 and RHLD2, as shown in Figure 27. It should be noted that

the additional current drawn has no effect on the rectified input voltage and therefore does not interfere with the

input power regulation control scheme.

Figure 28. Angle Detection Circuit and Hold Current Circuit Operation

To provide high efficiency, the hold circuit is enabled only when the presence of an external dimmer is detected

based on the FLT2 input. The ENHOLD signal is asserted and hold operation is permitted when VFLT2 falls below

1V. The hold operation is halted when VFLT2 rises above 1.2V. During dimming, the hold current is drawn during

the interval when rectified input voltage is below the VHOLD(TH), based on the external resistor RAC. The FET turn-

on is controlled by an internal comparator with a reference of 400mV (higher than angle detect reference), such

that hold current is always asserted before angle detect threshold VADET(TH). The hold circuit operation is

summarized in Figure 28. The hold trun-on threshold, VHOLD(TH) is given by

(16)

The hold current is based on the BIAS voltage and set by the sum of resistors RHLD1 and RHLD2,

(17)

In selecting the hold current level, it is critical to consider its impact on the average power dissipation and the

operating junction temperature of pass transistor, QPASS under worst case operating conditions. The current

should be limited to a safe value based on the pass transistor specifications or the ABS MAX rating of LM3447

(70mA). For best performance, it is recommended to set the hold current magnitude between 5mA and 20mA. A

capacitor, CHLD of 2.2μF to 10μF, from RHLD2 to GND is connected to limit the rate of change of input current

(diin/dt) caused by the step insertion of holding current. This prevents TRIAC based dimmers from misfiring at low

dimming level.

ANGLE DECODING CIRCUIT AND DIMMING

The LM3447 incorporates a linear decoding circuit that translates the sensed conduction angle into an internal

dimming command, VDIM. The conduction angle information, represented by the PWM signal at FLT1 output, is

processed by an external low pass filter consisting of resistor, RFLT and capacitor, CFLT, which attenuates the

twice line frequency component from the signal. The resulting analog signal at FLT2 is converted into the

dimming command by a linear analog processing circuit. The piecewise linear relationship between the FLT2

input and the dimming command is shown graphically in Figure 29.

Copyright © 2012, Texas Instruments Incorporated

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