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LAN9252/ML データシート(PDF) 264 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 264 Page - Microchip Technology |
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264 / 329 page  LAN9252 DS00001909A-page 264 2015 Microchip Technology Inc. 12.14.52 MII MANAGEMENT CONTROL/STATUS REGISTER Note 25: Write access depends upon the assignment of the MI interface (ECAT/PDI). Write access is generally blocked if the MII interface is busy (Busy bit of MII Management Control/Status Register = 1) Offset: 0510h-0511h Size: 16 bits Bits Description ECAT Type PDI Type Default 15 Busy 0: MI control state machine is idle 1: MI control state machine is active RO RO 0b 14 Command Error 0: Last command was successful 1: Invalid command or write command without write enable Note: Cleared with a valid command or by writing “00” to Command Register. RO RO 0b 13 Read Error 0: No read error 1: Read error occurred (PHY or register bi available) Note: Cleared by writing this register. R/W Note 25 R/W Note 25 0b 12:10 RESERVED RO RO 0b 9:8 Command Register Write: Initiate command. Read: Currently executed command See Note 26. Commands: 00: No command / MI Idle (clear error bits) 01: Read 10: Write 11: RESERVED (do not issue) R/W Note 25 R/W Note 25 00b 7:3 PHY Address Offset RO RO 00000b 2 MI Link Detection (Link configuration, link detection, registers PHY Port Status Registers) 0: Not available 1: MI Link Detection Active RO RO 0b Note 27 1 Management Interface Control 0: ECAT control only 1: MPDI control possible (MII Management ECAT Access State Register and MII Management PDI Access State Register) RO RO 1b 0 Write Enable 0: Write Disabled 1: Write Enabled Note: This bit is always 1 if PDI has MI control. (See Note 28) R/W Note 25 RO 0b |
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