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LAN9252/ML データシート(PDF) 265 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 265 Page - Microchip Technology |
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265 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 265 LAN9252 Note 26: Command Register bits (9:8) are self-clearing after the command is executed (Busy ends). Writing “00” to the Command Register bits will also clear the error bits 14:13 of this register. The Command Register bits (9:8) are cleared after the command is executed. Note 27: The default value of this field can be configured via EEPROM. This bit will be 0 and MI link detection disabled until the device is successfully configured from EEPROM. The EEPROM setting for MI link detection is only taken at the first EEPROM loading after power-on reset. Changing the EEPROM and manually reloading it will not affect the MI link detection enable status, even if the EEPROM could not be read initially. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information. Note 28: Write enable bit 0 is self-clearing at the SOF of the next frame (or end of the PDI access). Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.53 PHY ADDRESS REGISTER Note 29: Write access depends upon the assignment of the MI interface (ECAT/PDI). Write access is generally blocked if the MII interface is busy (Busy bit of MII Management Control/Status Register = 1) 12.14.54 PHY REGISTER ADDRESS REGISTER Note 30: Write access depends upon the assignment of the MI interface (ECAT/PDI). Write access is generally blocked if the MII interface is busy (Busy bit of MII Management Control/Status Register = 1) Offset: 0512h Size: 8 bits Bits Description ECAT Type PDI Type Default 7:5 RESERVED Write 0. RO RO 000b 4:0 PHY Address R/W Note 29 R/W Note 29 00000b Offset: 0513h Size: 8 bits Bits Description ECAT Type PDI Type Default 7:5 RESERVED Write 0. RO RO 000b 4:0 Address of PHY Register to be Read/Written R/W Note 30 R/W Note 30 00000b |
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