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LAN9252/ML データシート(PDF) 263 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 263 Page - Microchip Technology |
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263 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 263 LAN9252 12.14.50 EEPROM ADDRESS REGISTER Note: Write access depends upon the assignment of the EEPROM interface (ECAT/PDI). Write access is gener- ally blocked if the EEPROM interface is busy (Busy bit of EEPROM Control/Status Register = 1) Note: EtherCAT controls the SII EEPROM interface if the PDI EEPROM Control bit of the EEPROM Configuration Register is 0 and the Access to EEPROM bit of the EEPROM PDI Access State Register is 0. Otherwise, PDI controls the EEPROM interface. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.51 EEPROM DATA REGISTER Note: Write access depends upon the assignment of the EEPROM interface (ECAT/PDI). Write access is gener- ally blocked if the EEPROM interface is busy (Busy bit of EEPROM Control/Status Register = 1) Note: EtherCAT controls the SII EEPROM interface if the PDI EEPROM Control bit of the EEPROM Configuration Register is 0 and the Access to EEPROM bit of the EEPROM PDI Access State Register is 0. Otherwise, PDI controls the EEPROM interface. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. Offset: 0504h-0507h Size: 32 bits Bits Description ECAT Type PDI Type Default 31:0 EEPROM Address Bit 0: First word (16-bit) Bit 1: Second word ..... Note: Actually used EEPROM address bits: [9:0]: EEPROM size up to 16Kbit [17:0]: EEPROM size 32Kbit - 4Mbit [31:0]: EEPROM Emulation R/W R/W 00000000h Offset: 0508h-050Bh Size: 32 bits Bits Description ECAT Type PDI Type Default 31:16 EEPROM Read Data Data to be read from EEPROM, higher bytes RO RO 0000h 15:0 EEPROM Read/Write Data Data to be read from EEPROM, lower bytes or data to be written to EEPROM. R/W R/W 0000h |
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