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LAN9252/ML データシート(PDF) 289 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 289 Page - Microchip Technology |
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289 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 289 LAN9252 12.14.87 LATCH0 TIME POSITIVE EDGE REGISTER Note: Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which guaran- tees reading a consistent value. Clearing the Event LATCH0 Positive Edge bit of the LATCH0 Status Reg- ister depends upon setting of the Latch In Unit 0 bit of the Cyclic Unit Control Register. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.88 LATCH0 TIME NEGATIVE EDGE REGISTER Note: Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which guaran- tees reading a consistent value. Clearing the Event LATCH0 Negative Edge bit of the LATCH0 Status Reg- ister depends upon setting of the Latch In Unit 0 bit of the Cyclic Unit Control Register. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. Offset: 09B0h-09B7h Size: 64 bits Bits Description ECAT Type PDI Type Default 63:0 This register captures the System Time at the positive edge of the LATCH0 signal. Note: Reading this register clears the Event LATCH0 Posi- tive Edge bit of the LATCH0 Status Register RO RO 00000000h 00000000h Offset: 09B8h-09BFh Size: 64 bits Bits Description ECAT Type PDI Type Default 63:0 This register captures the System Time at the negative edge of the LACTH0 signal. Note: Reading this register clears the Event LATCH0 Neg- ative Edge bit of the LATCH0 Status Register RO RO 00000000h 00000000h |
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