LAN9252SLASHML datasheet(296/329 Pages) MICROCHIP

296 / 329 page

LAN9252

DS00001909A-page 296

 2015 Microchip Technology Inc.

14.0

CHIP MODE CONFIGURATION

The mode of the chip is controlled by the chip_mode_strap[1:0] (CHIP_MODE1/CHIP_MODE0) hard-strap as follows:

Once the mode of the chip is selected, the Process Data Interface (PDI) in use is selected by the PDI Control Register

(0x0140). The valid choices are as follows:

Note:

The mode of the chip as selected by the chip_mode_strap[1:0] hard-strap is not affected by the PDI selec-

tion.

Note:

Due to pin sharing, when the device is in 3 port mode, the only usable interface is SPI.

14.1

HBI Sub-Configuration

The PDI Configuration Register (0x0150) is used for the HBI configuration straps as shown in Table 12-

3, "EtherCAT Core EEPROM Configurable Registers".

The PDI Configuration Register (0x0150) is initialized from the contents of the EEPROM.

TABLE 14-1:

CHIP MODE SELECTION

CHIP_MODE[1:0]

Mode

2 port mode. Port 0 = PHY A, Port 1 = PHY B

RESERVED

3 port downstream mode. Port 0 = PHY A, Port 1 = PHY B, Port 2 = MII

3 port upstream mode. Port 0 = MII, Port 1 = PHY B, Port 2 = PHY A

TABLE 14-2:

PDI MODE SELECTION

PDI_SELECT

PDI MODE

0x04

DIG I/O

0x80

SPI

0x88

HBI Multiplexed 1 Phase 8-bit

0x89

HBI Multiplexed 1 Phase 16-bit

0x8A

HBI Multiplexed 2 Phase 8-bit

0x8B

HBI Multiplexed 2 Phase 16-bit

0x8C

HBI Indexed 8-bit

0x8D

HBI Indexed 16-bit

others

RESERVED

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