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LAN9252/ML データシート(PDF) 294 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 294 Page - Microchip Technology |
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294 / 329 page ![]() LAN9252 DS00001909A-page 294 2015 Microchip Technology Inc. 12.14.100 DIGITAL I/O INPUT DATA REGISTER Note: This register is part of the Process RAM address space. The Process RAM is also directly addressable via the EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA) and EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA). Note: Process Data RAM is only accessible if EEPROM was correctly loaded (PDI Operational/EEPROM Loaded Correctly bit of ESC DL Status Register = 1) Note: Digital I/O Input Data is written into the Process Data RAM at these addresses if a Digital I/O PDI with inputs is configured. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.101 PROCESS DATA RAM Note: Process Data RAM is only accessible if EEPROM was correctly loaded (PDI Operational/EEPROM Loaded Correctly bit of ESC DL Status Register = 1) Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. Offset: 1000h-1001h Size: 16 bits Bits Description ECAT Type PDI Type Default 15:0 Input Data R/W R/W Undefined Offset: 1000h-1FFFh Size: 4 KBytes Bits Description ECAT Type PDI Type Default - Process Data RAM (4 KBytes) R/W R/W Undefined |
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