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LAN9252/ML データシート(PDF) 293 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 293 Page - Microchip Technology |
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293 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 293 LAN9252 12.14.97 GENERAL PURPOSE OUTPUT REGISTER Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.98 GENERAL PURPOSE INPUT REGISTER Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.99 USER RAM Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. Offset: 0F10h-0F11h Size: 16 bits Bits Description ECAT Type PDI Type Default 15:0 General Purpose Output Data R/W R/W 0000h Offset: 0F18h-0F19h Size: 16 bits Bits Description ECAT Type PDI Type Default 15:0 General Purpose Input Data RO RO 0000h Offset: 0F80h-0FFFh Size: 128 Bytes Bits Description ECAT Type PDI Type Default - User RAM (128 Bytes) R/W R/W Undefined |
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