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LAN9252/ML データシート(PDF) 292 Page - Microchip Technology

部品番号 LAN9252/ML
部品情報  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9252/ML データシート(HTML) 292 Page - Microchip Technology

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LAN9252
DS00001909A-page 292
 2015 Microchip Technology Inc.
12.14.94 PRODUCT ID REGISTER
Note 40:
The value of “ss” is 0, 0, link_pol_strap_mii, tx_shift_strap[1:0], eeprom_size_strap, chip_mode_strap[1:0].
The value of “rrrr” is the current silicon revision.
Note:
For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the
highest address.
12.14.95 VENDOR ID REGISTER
Note:
For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the
highest address.
12.14.96 DIGITAL I/O OUTPUT DATA REGISTER
Note:
This register is bit-writable (using logical addressing).
Note:
For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the
highest address.
Offset:
0E00h-0E07h
Size:
64 bits
Bits
Description
ECAT
Type
PDI
Type
Default
63:0
Product ID
RO
RO
0000h
00ssh
9252h
rrrr
h
Note 40
Offset:
0E08h-0E0Fh
Size:
64 bits
Bits
Description
ECAT
Type
PDI
Type
Default
63:32
RESERVED
RO
RO
00000000h
31:0
Vendor ID
RO
RO
000004D8h
(Microchip)
Offset:
0F00h-0F01h
Size:
16 bits
Bits
Description
ECAT
Type
PDI
Type
Default
15:0
Output Data
R/W
RO
0000h



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