ADS5294IPFPR datasheet(35/82 Pages) TI2

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ADS5294

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SLAS776E – NOVEMBER 2011 – REVISED APRIL 2018

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9.3.5.2 Custom Filter Coefficients

The filter coefficients are also programmed, or customized, by the user. For custom coefficients, set the register

bit <FILTER COEFF SELECT> and load the coefficients (h0 to h11) in registers 0x5A to 0xB9, using the serial

interface as:

9.3.6 PLL Operation Versus LVDS Timing

The ADS5294 uses a PLL that automatically changes configuration to one of four states depending on the

sampling clock frequency. The clock frequency detection is automatic and each time the sampling frequency

crosses a threshold, the PLL changes configuration to a new state. The PLL remains in the new state for a range

of clock frequencies. To prevent unwanted toggling of PLL state around a threshold, the circuit has an built-in

hysteresis. The ADS5294 has three thresholds over the sampling clock frequency range from 10 MHz to 80 MHz

and can be in one of four states as shown by Figure 50.

Figure 50. PLL States Versus ADC Fs

Each threshold shifts by a small amount across temperature. On power up, depending on the clock frequency,

the PLL settles in one of four states. Later, as the system warms up, the PLL changes state once due to the shift

in the threshold across temperature.

9.3.6.1 Effect on Output Timings

The PLL state change has an effect on the output LVDS timings. In some settings, the set-up time decreases by

100 ps typically with a corresponding increase in the hold time.

In applications where a timing calibration occurs at the system level once after power-up, this subsequent

change of the PLL state is undesirable. The ADS5294 has register options to disable the automatic switch of the

PLL state based on frequency detected. To prevent this variation in output timing, disable the PLL from switching

states.

In addition to disabling the auto-switching, setting the PLL to the correct state is also required, depending on the

sample clock frequency used in the system. The following sequence of register writes must be followed exactly:

•

Step 1: Enable test-mode access by writing register data = 0x0010 in address 0x01 (for example: enable the

access to registers with address higher than 0xF0).

•

Step 2: Configure the PLL to the correct state depending on the clock frequency of operation and the

decimation factor, as per the following tables.

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