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ADS5294IPFPR データシート(PDF) 56 Page - Texas Instruments

部品番号 ADS5294IPFPR
部品情報  ADS5294 Octal-Channel 14-Bit 80-MSPS High-SNR and Low-Power ADC
PDF  82 Pages
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メーカー  TI2 [Texas Instruments]
ホームページ  https://www.ti.com
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ADS5294IPFPR データシート(HTML) 56 Page - Texas Instruments

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ADCLKp
LCLKp
OUTp
ADCLKp
LCLKp
OUTp
PHASE_DDR<1:0> = 00
ADCLKp
LCLKp
OUTp
PHASE_DDR<1:0> = 10
ADCLKp
LCLKp
OUTp
PHASE_DDR<1:0> = 01
PHASE_DDR<1:0> = 11
ADCLKp
LCLKp
OUTp
PHASE_DDR<1:0> = 10
56
ADS5294
SLAS776E – NOVEMBER 2011 – REVISED APRIL 2018
www.ti.com
Product Folder Links: ADS5294
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Copyright © 2011–2018, Texas Instruments Incorporated
•
k is set as described by the HPF_corner registers (one for each channel).
(4)
The HPF_EN bit in each register must be set to enable the HPF feature for each channel.
9.6.1.11 Bit-Clock Programmability
Table 19. Bit-Clock Programmability
ADDR.
(HEX)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
42
X
X
PHASE_DDR<1:0>
46
1
X
EN_SDR
46
1
X
FALL_SDR
The output interface of the ADS5294 is normally a DDR interface, with the LCLK rising edge and falling edge
transitions in the middle of alternate data windows. This default phase is shown in Figure 57.
Figure 57. Default Phase of LCLK
The phase of LCLK is programmed relative to the output frame clock and data using bits PHASE_DDR<1:0>.
The LCLK phase modes are shown in Figure 58.
Figure 58. Phase Programmability Modes for LCLK



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