L99UDL01 datasheet(77/88 Pages) STMICROELECTRONICS

77 / 88 page

DS12511 Rev 5

77/88

L99UDL01

Programmers guide

FLTx_y

Each integrated output has 2 bits assigned to communicate status.



Each current regulation loop provides information about an output going under current

regulation. This information is reported in fault register at the end of the Ton phase (just

before the braking phase).



An overcurrent flag occurs if the internal switch exceeds the maximum current allowed

(IOC_HS/IOC_LS). Due to how the active freewheeling circuit is activated, overcurrent

fault may only occur on the driving MOSFET. The freewheeling MOSFET will only show

an overcurrent if there is a short across the driving element while freewheeling.



Once an overcurrent fault is detected no CNR fault can be reported until the register is

reset with a read & clear command. An overcurrent event will latch off an output until

this register is read and cleared. An overcurrent fault has priority over CNR fault

regardless of the age of the fault.A CNR flag can be set if the driver is shorted. To

determine if a load is missing or the output is shorted an off-state diagnostic should be

performed.



CNR flag will not disable an output



CNR is not available when DBN_x = 1 (x = 1...6)

RD_Fail

Read fail

Cleared

FLT6_1

Output 6 Fault diagnostic bit 1

Cleared (1)

FLT6_0

Output 6 Fault diagnostic bit 0

Cleared (1)

FLT5_1

Output 5 Fault diagnostic bit 1

Cleared (1)

FLT5_0

Output 5 Fault diagnostic bit 0

Cleared (1)

FLT4_1

Output 4 Fault diagnostic bit 1

Cleared (1)

FLT4_0

Output 4 Fault diagnostic bit 0

Cleared (1)

FLT3_1

Output 3 Fault diagnostic bit 1

Cleared (1)

FLT3_0

Output 3 Fault diagnostic bit 0

Cleared (1)

FLT2_1

Output 2 Fault diagnostic bit 1

Cleared (1)

FLT2_0

Output 2 Fault diagnostic bit 0

Cleared (1)

FLT1_1

Output 1 Fault diagnostic bit 1

Cleared (1)

FLT1_0

Output 1 Fault diagnostic bit 0

Cleared (1)

0 LSB

Parity

Parity bit

1. It is recommended, if a read and clear operation is performed, that all bits for that output (or paralleled outputs) be cleared.

Otherwise there could be confusion as to the reported fault.

Table 52. 10H register bit description (continued)

Bit No.

Function

Level

State after Read

& Clear

Default

(after POR)

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