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MPC8309CVMADDC データシート(PDF) 72 Page - NXP Semiconductors

部品番号 MPC8309CVMADDC
部品情報  PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications
PDF  81 Pages
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MPC8309CVMADDC データシート(HTML) 72 Page - NXP Semiconductors

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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
72
Freescale Semiconductor
Thermal
24 Thermal
This section describes the thermal specifications of the MPC8309.
24.1
Thermal Characteristics
The following table provides the package thermal characteristics for the 369, 19
 19 mm MAPBGA of
the MPC8309.
24.1.1
Thermal Management Information
For the following sections, PD =(VDD  IDD)+PI/O, where PI/O is the power dissipation of the I/O
drivers.
24.1.2
Estimation of Junction Temperature with Junction-to-Ambient
Thermal Resistance
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
TJ =TA +(R
JA  PD)
Eqn. 1
where:
TJ = junction temperature (C)
Table 64. Package Thermal Characteristics for MAPBGA
Characteristic
Board type
Symbol
Value
Unit
Notes
Junction-to-ambient natural convection
Single-layer board (1s)
RJA
40
°C/W
1, 2
Junction-to-ambient natural convection
Four-layer board (2s2p)
RJA
25
°C/W
1, 2, 3
Junction-to-ambient (@200 ft/min)
Single-layer board (1s)
RJMA
33
°C/W
1, 3
Junction-to-ambient (@200 ft/min)
Four-layer board (2s2p)
RJMA
22
°C/W
1, 3
Junction-to-board
RJB
15
°C/W
4
Junction-to-case
RJC
9°C/W
5
Junction-to-package top
Natural convection
JT
2°C/W
6
Notes:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.



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