RMLD232UAW datasheet(2/50 Pages) EMLSI

2 / 50 page

Rev 0.7

64Mb Low Power DDR SDRAM

Advanced

2M x 32 Low Power DDR SDRAM

Features

1.8V power supply, 1.8V I/O power

Double-data-rate architecture; two data transfers per clock cycle

Bidirectional data strobe(DQS)

Four banks operation

Differential clock inputs(CK and CK)

MRS cycle with address key programs

- CAS Latency ( 3 )

- Burst Length ( 2, 4, 8, 16 )

- Burst Type (Sequential & Interleave)

- Partial Self Refresh Type ( Full, 1/2, 1/4 array )

- Internal Temperature Compensated Self Refresh

- Driver strength ( 1, 1/2, 1/4, 1/8 )

Deep Power Down Mode

All inputs except data & DM are sampled at the positive going edge of the system clock(CK).

Data I/O transactions on both edges of data strobe, DM for masking.

Edge aligned data output, center aligned data input.

No DLL; CK to DQS is not synchronized.

DM0 - DM3 for write masking only.

15.6

auto refresh duty cycle.

Opreating Frequency

*CL : CAS Latency

Column Address Configuration

DM is internally loaded to match DQ and DQS identically.

DDR266

DDR222

Speed @CL2

Speed @CL3

133

111

Organization

Row Address

Column Address

A0 ~ A10

A0-A7

General Wafer Specifications

Process Technology : 0.125um Trench DRAM Process

Wafer thickness : 725 +/- 25um

Wafer Diameter : 8-inch

RMLD232UAW データシート(PDF) 2 Page - Emerging Memory & Logic Solutions Inc

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