E2000 datasheet(26/104 Pages) INTEL

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Electrical Specifications

Datasheet

2.7.3.1

GTL+ Front Side Bus Specifications

In most cases, termination resistors are not required as these are integrated into the

processor silicon. See Table 9 for details on which GTL+ signals do not include on-die

termination.

Valid high and low levels are determined by the input buffers by comparing with a

reference voltage called GTLREF. Table 14 lists the GTLREF specifications. The GTL+

reference voltage (GTLREF) should be generated on the system board using high

precision voltage divider circuits.

Table 13.

CMOS Signal Group DC Specifications

Symbol

Parameter

Min

Max

Unit

Notes1

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

VIL

Input Low Voltage

-0.10

VTT * 0.30

2, 3

VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low

value.

The VTT referred to in these specifications refers to instantaneous VTT.

VIH

Input High Voltage

VTT * 0.70

VTT + 0.10

4, 5, 3

VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high

value.

VIH and VOH may experience excursions above VTT. However, input signal drivers must comply

with the signal quality specifications.

VOL

Output Low Voltage

-0.10

VTT * 0.10

VOH

Output High Voltage

0.90 * VTT

VTT + 0.10

6, 5, 3

All outputs are open drain.

IOL

Output Low Current

1.70

4.70

3, 7

IOL is measured at 0.10 * VTT. IOH is measured at 0.90 * VTT.

IOH

Output High Current

1.70

4.70

3, 7

ILI

Input Leakage Current

N/A

± 100

µA

Leakage to VSS with land held at VTT.

ILO

Output Leakage Current

N/A

± 100

µA

Leakage to VTT with land held at 300 mV.

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