STW4811MBRATSLASHHF datasheet(43/85 Pages) STMICROELECTRONICS

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STw4811M/STw4811N

Functional description

CD00131784

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4.3.6

VAUX

This LDO is dedicated either to the multimedia processor input/output signals or to the

auxiliary devices. Power supply values are 1.5, 1.8, 2.5, 2.8 V with 150 mA full load and

0.5 mA in sleep mode. In case of 1.5 V on the output, this LDO can be supplied by using

VIO_VMEM DC/DC converter (1.8 V). One pad feed-back is used.

Main features:

●

Programmable output voltage, 4 levels

(‘vaux_sel[1:0]’ bits of

power control register - Table 23)

●

Three power domains:

–

‘High power mode’ when multimedia processor is in run mode, 150 mA full load

–

‘Low current mode’ when multimedia processor is in sleep mode, 0.5 mA current

capability.

Fast switching from low current to high power mode.

Note:

The definition of sleep mode is given in 4.2.3: Sleep mode section.

–

‘Power down mode’ or ‘standby mode’ when regulator is switched off, no power

consumption (‘pdn_vaux’ bit of

configuration 1 register - Table 18).

4.3.7

Power supply monitoring

This block monitors the VCORE and VIO_VMEM output voltage. If VCORE or VIO_VMEM

drop below the threshold, the multimedia processor is reset, through PORn output ball.

In high power mode, this feature can be disabled by setting ‘en_monitoring’ bit of

power

control register to “0” (Table 25).

When VCORE programmed value changes, ‘vcore_available’ bit (

Table 29) gives the status

of VCORE output supply value and informs the APE that the expected output voltage is

reached, this bit is a read only bit and is reset after an APE read operation.

Figure 11 describes ‘vcore_available’ bit behavior.

Figure 11.

‘vcore_available’ bit behavior

Vcore

vcore_available bit

read operation to reset bit

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