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CY8C53 データシート(PDF) 50 Page - Cypress Semiconductor

部品番号 CY8C53
部品情報  Programmable System-on-Chip (PSoC) DC to 67 MHz operation
PDF  106 Pages
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メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C53 データシート(HTML) 50 Page - Cypress Semiconductor

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PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Document Number: 001-66237 Rev. *A
Page 50 of 106
8.4 Opamps
The CY8C53 family of devices contain two general purpose
opamps.
Figure 8-5. Opamp
The opamp is uncommitted and can be configured as a gain
stage or voltage follower on external or internal signals.
See Figure 8-6. In any configuration, the input and output signals
can all be connected to the internal global signals and monitored
with
an
ADC,
or
comparator.
The
configurations
are
implemented with switches between the signals and GPIO pins.
Figure 8-6. Opamp Configurations
The opamp has three speed modes, slow, medium, and fast. The
slow mode consumes the least amount of quiescent power and
the fast mode consumes the most power. The inputs are able to
swing rail-to-rail. The output swing is capable of rail-to-rail
operation at low current output, within 50 mV of the rails. When
driving high current loads (about 25 mA) the output voltage may
only get within 500 mV of the rails.
8.5 Programmable SC/CT Blocks
The
CY8C53
family
of
devices
contains
two
switched
capacitor/continuous time (SC/CT) blocks in a device. Each
switched capacitor/continuous time block is built around a single
rail-to-rail high bandwidth opamp.
Switched capacitor is a circuit design technique that uses
capacitors plus switches instead of resistors to create analog
functions. These circuits work by moving charge between
capacitors
by
opening
and
closing
different
switches.
Nonoverlapping in phase clock signals control the switches, so
that not all switches are ON simultaneously.
The PSoC Creator tool offers a user friendly interface, which
allows you to easily program the SC/CT blocks. Switch control
and clock phase control configuration is done by PSoC Creator
so users only need to determine the application use parameters
such as gain, amplifier polarity, VREF connection, and so on.
The same opamps and block interfaces are also connectable to
an array of resistors which allows the construction of a variety of
continuous time functions.
The opamp and resistor array is programmable to perform
various analog functions including
Naked Operational Amplifier - Continuous Mode
Unity-Gain Buffer - Continuous Mode
Programmable Gain Amplifier (PGA) - Continuous Mode
Transimpedance Amplifier (TIA) - Continuous Mode
Up/Down Mixer - Continuous Mode
Sample and Hold Mixer (NRZ S/H) - Switched Cap Mode
First Order Analog to Digital Modulator - Switched Cap Mode
8.5.1 Naked Opamp
The Naked Opamp presents both inputs and the output for
connection to internal or external signals. The opamp has a unity
gain bandwidth greater than 6.0 MHz and output drive current up
to 650 µA. This is sufficient for buffering internal signals (such as
DAC outputs) and driving external loads greater than 7.5 kohms.
8.5.2 Unity Gain
The Unity Gain buffer is a Naked Opamp with the output directly
connected to the inverting input for a gain of 1.00. It has a -3 dB
bandwidth greater than 6.0 MHz.
Opamp
VREF
GPIO
GPIO
=
Analog Switch
GPIO
Analog
Global Bus
Analog
Internal Bus
Analog
Global Bus
Opamp
Vout to Pin
Vin
Vout to GPIO
Vp to GPIO
b) External Uncommitted
Opamp
a) Voltage Follower
Vout to Pin
Vp
Vn
To Internal Signals
c) Internal Uncommitted
Opamp
Vn to GPIO
GPIO Pin
Opamp
Opamp
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