CY8C53_11 datasheet(6/106 Pages) CYPRESS

6 / 106 page

PRELIMINARY

PSoC® 5: CY8C53 Family Datasheet

Document Number: 001-66237 Rev. *A

Page 6 of 106

Figure 2-1. 68-Pin QFN Part Pinout[3]

(GPIO) P2[6]

(GPIO) P2[7]

(SIO) P12[4]

(SIO) P12[5]

Vssb

Ind

Vboost

Vbat

Vssd

XRES

(SWDIO, GPIO) P1[0]

(SWDCK, GPIO) P1[1]

(GPIO) P1[2]

(SWV, GPIO) P1[3]

(GPIO) P1[4]

(GPIO) P1[5]

Vddio1

P0[3] (GPIO, OpAmp0-/Extref0)

P0[2] (GPIO, OpAmp0+)

P0[1] (GPIO, OpAmp0out)

P0[0] (GPIO, OpAmp2out)

P12[3] (SIO)

P12[2] (SIO)

Vssd

Vdda

Vssa

Vcca

P15[3] (GPIO, kHz XTAL: Xi)

P15[2] (GPIO, kHz XTAL: Xo)

P12[1] (SIO)

P12[0] (SIO)

P3[7] (GPIO, OpAmp3out)

P3[6] (GPIO, OpAmp1out)

Vddio3

QFN

(Top View)

Lines show Vddio

to I/O supply

association

Notes

2. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.

3. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to

ground, it should be electrically floated and not connected to any other signal.

[+] Feedback

CY8C53 データシート(PDF) 6 Page - Cypress Semiconductor

CY8C53 データシート(HTML) 6 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード