CY8C53_11 datasheet(12/106 Pages) CYPRESS

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PSoC® 5: CY8C53 Family Datasheet

Document Number: 001-66237 Rev. *A

Page 12 of 106

4.2 Cache Controller

The CY8C53 family adds an instruction cache between the CPU

and the flash memory. This guarantees a faster instruction

execution rate. The flash cache also reduces system power

consumption by requiring less frequent flash access.

4.3 DMA and PHUB

The PHUB and the DMA controller are responsible for data

transfer between the CPU and peripherals, and also data

transfers between peripherals. The PHUB and DMA also control

device configuration during boot. The PHUB consists of:

A central hub that includes the DMA controller, arbiter, and

router

Multiple spokes that radiate outward from the hub to most

peripherals

There are two PHUB masters: the CPU and the DMA controller.

Both masters may initiate transactions on the bus. The DMA

channels can handle peripheral communication without CPU

intervention. The arbiter in the central hub determines which

DMA channel is the highest priority if there are multiple requests.

4.3.1 PHUB Features

CPU and DMA controller are both bus masters to the PHUB

Eight Multi-layer AHB Bus parallel access paths (spokes) for

peripheral access

Simultaneous CPU and DMA access to peripherals located on

different spokes

Simultaneous DMA source and destination burst transactions

on different spokes

Supports 8-, 16-, 24-, and 32-bit addressing and data

4.3.2 DMA Features

24 DMA channels

Each channel has one or more transaction descriptors (TDs)

to configure channel behavior. Up to 127 total TDs can be

defined

TDs can be dynamically updated

Eight levels of priority per channel

Any digitally routable signal, the CPU, or another DMA channel,

can trigger a transaction

Each channel can generate up to two interrupts per transfer

Transactions can be stalled or canceled

Supports transaction size of infinite or 1 to 64k bytes

Large transactions may be broken into smaller bursts of 1 to

127 bytes

TDs may be nested and/or chained for complex transactions

4.3.3 Priority Levels

The CPU always has higher priority than the DMA controller

when their accesses require the same bus resources. Due to the

system architecture, the CPU can never starve the DMA. DMA

channels of higher priority (lower priority number) may interrupt

current DMA transfers. In the case of an interrupt, the current

transfer is allowed to complete its current transaction. To ensure

latency limits when multiple DMA accesses are requested

simultaneously, a fairness algorithm guarantees an interleaved

minimum percentage of bus bandwidth for priority levels 2

through 7. Priority levels 0 and 1 do not take part in the fairness

algorithm and may use 100% of the bus bandwidth. If a tie occurs

on two DMA requests of the same priority level, a simple round

robin method is used to evenly share the allocated bandwidth.

The round robin allocation can be disabled for each DMA

channel, allowing it to always be at the head of the line. Priority

levels 2 to 7 are guaranteed the minimum bus bandwidth shown

in Table 4-4 after the CPU and DMA priority levels 0 and 1 have

satisfied their requirements.

When the fairness algorithm is disabled, DMA access is granted

based solely on the priority level; no bus bandwidth guarantees

are made.

4.3.4 Transaction Modes Supported

The flexible configuration of each DMA channel and the ability to

chain multiple channels allow the creation of both simple and

complex use cases. General use cases include, but are not

limited to:

4.3.4.1

Simple DMA

In a simple DMA case, a single TD transfers data between a

source and sink (peripherals or memory location). The basic

timing diagrams of DMA read and write cycles are shown in

Figure 4-2. For more description on other transfer modes, refer

to the Technical Reference Manual.

Table 4-3. PHUB Spokes and Peripherals

PHUB Spokes

Peripherals

SRAM

IOs, PICU

PHUB local configuration, Power manager,

Clocks, IC, EEPROM, Flash programming

interface

Analog interface and trim, Decimator

USB, CAN, I2C, Timers, Counters, and PWMs

Reserved

UDBs group 1

UDBs group 2

Table 4-4. Priority Levels

Priority Level

% Bus Bandwidth

100.0

50.0

25.0

12.5

6.2

3.1

1.5

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