CY8C53_11 datasheet(103/106 Pages) CYPRESS

103 / 106 page

PRELIMINARY

PSoC® 5: CY8C53 Family Datasheet

Document Number: 001-66237 Rev. *A

Page 103 of 106

15. Reference Documents

PSoC® 3, PSoC® 5 Architecture TRM

PSoC® 5 Registers TRM

PLA

programmable logic array

PLD

programmable logic device, see also PAL

PLL

phase-locked loop

PMDD

package material declaration data sheet

POR

power-on reset

PRS

pseudo random sequence

port read data register

PSoC®

Programmable System-on-Chip™

PSRR

power supply rejection ratio

PWM

pulse-width modulator

RAM

random-access memory

RISC

reduced-instruction-set computing

RMS

root-mean-square

RTC

real-time clock

RTL

RTR

remote transmission request

receive

SAR

successive approximation register

SC/CT

switched capacitor/continuous time

SCL

I2C serial clock

SDA

I2C serial data

S/H

sample and hold

SIO

special input/output, GPIO with advanced

features. See GPIO.

SNR

signal-to-noise ratio

SOC

start of conversion

SOF

start of frame

Table 14-1. Acronyms Used in this Document

(continued)

Acronym

Description

SPI

Serial Peripheral Interface, a communications

protocol

slew rate

SRAM

static random access memory

SRES

software reset

SWD

serial wire debug, a test protocol

SWV

single-wire viewer

transaction descriptor, see also DMA

THD

total harmonic distortion

TIA

transimpedance amplifier

TRM

technical reference manual

TTL

transistor-transistor logic

transmit

UART

Universal Asynchronous Transmitter Receiver, a

communications protocol

UDB

universal digital block

USB

Universal Serial Bus

USBIO

USB input/output, PSoC pins used to connect to

a USB port

VDAC

voltage DAC, see also DAC, IDAC

WDT

watchdog timer

WOL

write once latch, see also NVL

WRES

watchdog timer reset

XRES

external reset I/O pin

XTAL

crystal

Table 14-1. Acronyms Used in this Document

(continued)

Acronym

Description

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