DAC5687MPZPEP datasheet(27/75 Pages) TI1

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DAC5687-EP

SGLS333 – JUNE 2006

Table 2. inv_plllock Bit Modes (continued)

PLLVDD

dual_clk

inv_pllock

fifo_bypass

DESCRIPTION

0 V

Not a valid setting. Do not use.

3.3 V

Internal PLL enabled, CLK1/CLK1C input differential clock is

used to latch the input data. The FIFO is always disabled in this

mode.

3.3 V

Not a valid setting. Do not use.

BIT 7

BIT 0

qflag

interl

dual_clk

twos

rev_abus

rev_bbus

fir_bypass

full_bypass

qflag:

When set, the QFLAG input pin operates as a B sample indicator when interleaved data is

enabled. When cleared, the TXENABLE rising determines the A/B timing relationship.

interl:

When set, interleaved input data mode is enabled; both A and B data streams are input at the

DA(15:0) input pins.

dual_clk:

Only used when the PLL is disabled. When set, two differential clocks are used to input the data to

the chip; CLK1/CLK1C is used to latch the input data into the chip and CLK2/CLK2C is used as the

DAC sample clock.

twos:

When set, input data is interpreted as 2’s complement. When cleared, input data is interpreted as

offset binary.

rev_abus:

When cleared, DA input data MSB to LSB order is DA(15) = MSB and DA(0) = LSB. When set, DA

input data MSB to LSB order is reversed, DA(15) = LSB and DA(0) = MSB.

rev_bbus:

When cleared, DB input data MSB to LSB order is DB(15) = MSB and DB(0) = LSB. When set, DB

input data MSB to LSB order is reversed, DB(15) = LSB and DB(0) = MSB.

fir_bypass: When set, all interpolation filters are bypassed (interp(1:0) setting has no effect). QMC and NCO

blocks are functional in this mode up to f

dac = 250 MHz, limited by the input datarate.

full_bypass: When set, all filtering, QMC and NCO functions are bypassed.

BIT 7

BIT 0

nco

nco_gain

qmc

cm_mode(3:0)

invsinc

nco:

When set, the NCO is enabled.

nco_gain:

When set, the data output of the NCO is increased by 2

×.

qmc:

Quadrature modulator gain and phase correction is enabled when set.

cm_mode(3:0): Controls f

DAC/2 or fDAC/4 mixer modes for the coarse mixer block.

Table 3. Coarse Mixer Sequences

cm_mode(3:0)

Mixing Mode

Sequence

00XX

No mixing

0100

fDAC/2

DAC A = {–A +A –A +A

…}

DAC B = {–B +B –B +B

…}

0101

fDAC/2

DAC A = {–A +A –A +A

…}

DAC B = {+B –B +B –B

…}

0110

fDAC/2

DAC A = {+A –A +A –A

…}

DAC B = {–B +B –B +B

…}

0111

fDAC2

DAC A = {+A –A +A –A

…}

DAC B = {+B –B +B –B

…}

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