DAC5687MPZPEP datasheet(46/75 Pages) TI1

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PHSTR

QFLAG

TXENABLE

DB(15)

DA(15)

sync_fifo = “100”

DA(15) first rising edge

PLLLOCK

MUX

CLK1

CLK1C

{PLLVDD, inv_plllock, dual_clk}

clk_in

MUX

clock

generator

PLL VCO

clk_out

sync

= “100”

sync_fifo(2:0)

000

001

010

011

100

101

110

111

resync_fifo_in

CLK2

CLK2C

resync_fifo_out

Even/Odd Input Mode

Synchronization

DAC5687-EP

SGLS333 – JUNE 2006

All possible sync sources are registered with clk_in and then passed through a synchronous rising edge

detector.

Figure 51. DAC5687 FIFO Synchronization Source Logic

For example, if TXENABLE is selected as the sync source, a low-to-high transition on the TXENABLE pin

causes the pointers to be initialized.

Once initialized, the FIFO input pointer advances using clk_in and the output pointer advances using clk_out,

providing an elastic buffering effect. The phase relationship between clk_in and clk_out can wander or drift until

the output pointer overruns the input pointer or vice versa.

The DAC5687 has a double data rate input mode that allows both input ports to be used to multiplex data onto

one DAC channel (A). In the Even/Odd mode, the FIR3 filter can be used to interpolate the data by 2x. The

even/odd input mode is enabled by setting half_rate in CONFIG3. The maximum input rate for each port is 250

MSPS, for a combined rate of 500 MSPS.

The DAC5687 has several digital circuits that can be synchronized to a known state. The circuits that can be

synchronized are the fine mixer (NCO), coarse mixer (fixed fs/2 or fs/4 mixer), the FIFO input and output

pointers, and the internal clock divider.

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