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align +

CLK2

* 0.5 ns

CLK2

CLK1

DA[15:0]

DB[15:0]

∆ < talign

CLK1

DA[15:0]

DB[15:0]

Input FIFO

DAC5687-EP

SGLS333 – JUNE 2006

where fCLK2 is the clock frequency at CLK2. For example, talign = 0.5 ns at fCLK2 = 500 MHz and 1.5 ns at fCLK2 =

250 MHz.

If the FIFO is enabled (inv_plllock set) in dual clock mode, then CLK1 is only used as an input latch (Figure 49)

and is independent from the internal divided clock generated from CLK2/CLK2C and there is no alignment

specification. However, the FIFO needs to be synchronized by one of the methods listed in SYNC_CNTL

between CLK1 and the internally divided clock.

Figure 48. Dual Clock Mode Without FIFO

Figure 49. Dual Clock Mode With FIFO

The CDC7005 from Texas Instruments is recommended for providing phase aligned clocks at different

frequencies for this application.

In DAC clock mode, where the DAC5687 is clocked at the DAC update rate, the DAC5687 has an optional input

FIFO that allows latching of DA[15:0], DB[15:0] and PHSTR based on a user provided CLK1/CLK1C input or the

input data rate clock provided to the PLLLOCK pin. The FIFO can be bypassed by setting register fifo_bypass

in CONFIG0 to 1.

The input interface FIFO incorporates a four sample register file, an input pointer, and an output pointer.

Initialization of the FIFO pointers can be programmed to one of seven different sources.

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