LM2512A

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SNLS269B – AUGUST 2007 – REVISED MAY 2013

SWITCHING CHARACTERISTICS (continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

SPI Data Active (SDA_device)

See Figure 16

0

50

ns

SPI Data Tri-State

0

50

ns

(SDA_device)

RECOMMENDED INPUT TIMING REQUIREMENTS (PCLK AND SPI)

Over recommended operating supply and temperature ranges unless otherwise specified.

(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

PIXEL CLOCK (PCLK)

Pixel Clock Frequency

3 MD Lane, (4X)

7.5

22.5

MHz

2 MD Lane, (6X)

5

15

MHz

Pixel Clock Duty Cycle

30

50

70

%

Transition Time

2

>2

ns

Clock Stop Gap

PCLK

4

2

cycles

SPI INTERFACE

SCL Frequency

WRITE

10

MHz

READ

6.67

MHz

CSX Set Time

60

ns

SI Set Time

See Figure 15

30

ns

SI Hold Time

30

ns

SCL Pulse Width High

WRITE

35

ns

READ

60

ns

See Figure 15,

Figure 16

SCL Pulse Width Low

WRITE

35

ns

READ

60

ns

SCL Rise Time

5

ns

SCL Fall Time

5

ns

SI Hold Time

See Figure 15

30

ns

CSX Hold Time

65

ns

CSX OFF Time

100

ns

(1)

(2)

Maximum transition time is a function of clock rate and should be less than 30% of the clock period to preserve signal quality.

(3)

This is a functional parameter and is specified by design or characterization.

(4)

This is the minimum time that the PCLK needs to be held off for in order for the device to be reset. Once PCLK is reapplied, a PLL Lock

is required and start up sequence before video data is serialized.

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