MC

MD0

MDn

LM2512A

www.ti.com

SNLS269B – AUGUST 2007 – REVISED MAY 2013

SERIAL BUS TIMING

Data valid is relative to both edges of a RGB transaction as shown in Figure 8. Data valid is specified as: Data

Valid before Clock, Data Valid after Clock, and Skew between data lines should be less than 500ps.

Figure 8. Dual Link Timing

SERIAL BUS PHASES

There are three bus phases on the MPL serial bus. These are determined by the state of the MC and MD lines.

The MPL bus phases are shown in Table 1.

The LM2512A supports MPL Level 0 Enhanced Protocol with a Class 0 PHY.

Name

MC State

MDn State

Phase Description

Pre-Phase

Post-Phase

OFF (O)

0

0

Link is Off

A, or LU

LU

LINK-UP (LU)

0LHL

000L

Start Up Pulse

O

A or O

Active (A)

A

X

Streaming Data

LU

O

(1)

Notes on MC/MD Line State:

0 = no current (off)

L = Logic Low—The higher level of current on the MC and MD lines

H = Logic High—The lower level of current on the MC and MD lines

X = Low or High

A = Active Clock

SERIAL BUS START UP TIMING

In the Serial Bus OFF phase, SER line drivers for MDs and MC are turned off such that zero current flows over

the MPL lines. On the SER side, when the PD* input pin is de-asserted (driven High), or with PD* = High and the

PCLK is turned on, the SER will power up its bias block during t0.

The SER will next drive the MC line to the logic Low (5I current) state for 200 PCLK cycles (t1). The DES devices

detects the current flowing in the MC line, and powers up its analog circuit blocks (or alternately is controlled by

its PD* input pin - device specific).

The SER then drives the MC line to a logic High (1I current) for 20 PCLK cycles (t2). On the MC low-to-high

transition, the DES samples the current and optimizes it current sources to match that of the drivers.

The MC is now driven to a logic Low (5I current) for 8 PCLK cycles (t3).

Next the SER PLL is locked to the PCLK. A hold off counter of 600 PCLK cycles is used to hold off until the PLL

has locked and is stable (t4). At this point, streaming RGB information is now sent across the MPL link.

Link-Up is shown in Figure 9. The MC and MDn signals are current waveforms. Data at the DES output will

appear a latency delay later.

Copyright © 2007–2013, Texas Instruments Incorporated

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