MD0

MPL-1 Deserializer

LM2512A Serializer

[Supply, Configuration pins,

and bypass caps. and grounding not shown]

PD*

MD1

MC

MD2

PLL

Apps

Processor

---

Graphics

Processor

---

Baseband

Processor

B[5:0]

VS

HS

DE

PCLK

R[5:0]

G[5:0]

RGB Display

VGA

at 18-Bit Color Depth

PD*

S

P

I

B[7:0]

VS

HS

DE

PCLK

R[7:0]

G[7:0]

D

i

t

h

e

r

Three

256 X

8

LUT

P

2

S

SPI_CSX

SPI_SDA

SPI_SCL

LM2512A

www.ti.com

SNLS269B – AUGUST 2007 – REVISED MAY 2013

LM2512A Mobile Pixel Link (MPL-1), 24-Bit RGB Display Interface Serializer with Optional

Dithering and Look Up Table

Check for Samples: LM2512A

1

FEATURES

DESCRIPTION

The LM2512A is a MPL Serializer (SER) that

2

•

24-bit RGB Interface Support up to 640 x 480

performs a 24-bit to 18-bit Dither operation and

VGA Format

serialization of the video signals to Mobile Pixel link

•

Optional 24 to 18-bit Dithering

(MPL) levels on only 3 or 4 active signals. An optional

•

Optional Look Up Table for Independent Color

Look Up Table (Three X 256 X 8 bit RAM) is also

provided for independent color correction. 18-bit

Correction

Bufferless or partial buffer displays from QVGA (320

•

MPL-1 Physical Layer

x 240) up to VGA (640 x 480) pixels can utilize a 24-

•

SPI Interface for Look Up Table Control and

bit video source.

Loading

The interconnect is reduced from 28 signals to only 3

•

Low Power Consumption & Powerdown State

or 4 active signals with the LM2512A and companion

•

Level Translation Between Host and Display

deserializer easing flex interconnect design, size

constraints and cost.

•

Optional Auto Power Down on STOP PCLK

•

Frame Sequence Bits Auto Resync upon Data

The LM2512A SER resides by the application,

or Clock Error

graphics or baseband processor and translates the

wide parallel video bus from LVCMOS levels to serial

•

1.6V to 2.0V Core / Analog Supply Voltage

Mobile Pixel Link levels for transmission over a flex

•

1.6V to 3.0V I/O Supply Voltage Range

cable (or coax) and PCB traces to the DES located

near or in the display module.

SYSTEM BENEFITS

When in Power_Down, the SER is put to sleep and

•

Dithered Data Reduction

draws less than 10

μA. The link can also be powered

down by stopping the PCLK (DES dependant) or by

•

Independent RGB Color Correction

the PD* input pins.

•

24-bit Color Input

The LM2512A provides enhanced AC performance

•

Small Interface, Low Power and Low EMI

over the LM2512. It implements the physical layer of

•

Intrinsic Level Translation

the MPL-1 and uses a single-ended current-mode

transmission.

Typical 3 MD Lane Application Diagram - Bridge Chip

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2007–2013, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.