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データシートサーチシステム |
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データシートサーチシステム |
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MPC875 データシート(PDF) 44 Page - Freescale Semiconductor, Inc |
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MPC875 データシート(HTML) 44 Page - Freescale Semiconductor, Inc |
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44 / 84 page  MPC875/MPC870 Hardware Specifications, Rev. 3.0 44 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor IEEE 1149.1 Electrical Specifications Figure 35 provides the reset timing for the debug port configuration. Figure 35. Reset Timing—Debug Port Configuration 12 IEEE 1149.1 Electrical Specifications Table 16 provides the JTAG timings for the MPC875/870 shown in Figure 36 to Figure 39. Table 16. JTAG Timing Num Characteristic All Frequencies Unit Min Max J82 TCK cycle time 100.00 — ns J83 TCK clock pulse width measured at 1.5 V 40.00 — ns J84 TCK rise and fall times 0.00 10.00 ns J85 TMS, TDI data setup time 5.00 — ns J86 TMS, TDI data hold time 25.00 — ns J87 TCK low to TDO data valid — 27.00 ns J88 TCK low to TDO data invalid 0.00 — ns J89 TCK low to TDO high impedance — 20.00 ns J90 TRST assert time 100.00 — ns J91 TRST setup time to TCK low 40.00 — ns J92 TCK falling edge to output valid — 50.00 ns J93 TCK falling edge to output valid out of high impedance — 50.00 ns J94 TCK falling edge to output high impedance — 50.00 ns J95 Boundary scan input valid to TCK rising edge 50.00 — ns J96 TCK rising edge to boundary scan input invalid 50.00 — ns CLKOUT SRESET DSCK, DSDI R70 R82 R80 R80 R81 R81 |
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