MPC875 datasheet(59/84 Pages) FREESCALE

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MPC875/MPC870 Hardware Specifications, Rev. 3.0

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Freescale Semiconductor

CPM Electrical Characteristics

Figure 54. HDLC Bus Timing Diagram

13.7 Ethernet Electrical Specifications

Table 24 provides the Ethernet timings as shown in Figure 55 to Figure 57.

Table 24. Ethernet Timing

Num

Characteristic

All

Frequencies

Unit

Min

Max

120

CLSN width high

—

121

RCLK3 rise/fall time

—

122

RCLK3 width low

—

123

RCLK3 clock period 1

120

124

RXD3 setup time

—

125

RXD3 hold time

—

126

RENA active delay (from RCLK3 rising edge of the last data bit)

—

127

RENA width low

100

—

128

TCLK3 rise/fall time

—

129

TCLK3 width low

—

130

TCLK3 clock period1

101

131

TXD3 active delay (from TCLK3 rising edge)

—

132

TXD3 inactive delay (from TCLK3 rising edge)

6.5

TCLK3

CTS3

(Echo Input)

102

100

104

TxD3

(Output)

102

101

RTS3

(Output)

103

104

107

105

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