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LM2502 データシート(PDF) 5 Page - Texas Instruments |
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LM2502 データシート(HTML) 5 Page - Texas Instruments |
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5 / 31 page  LM2502 www.ti.com SNLS176L – JANUARY 2004 – REVISED MAY 2013 Pin Descriptions (continued) Description No. Pin Name I/O, Type(1) of Pins Master (SER) Slave (DES) CS1* 1 IO, ChipSelect1* – Input ChipSelect1* – Output LVCMOS H = Ignored H = Ignored L = Active L = Active CS2* 1 IO, ChipSelect2* – Input ChipSelect2* – Output LVCMOS H = Ignored H = Ignored L = Active L = Active A/D (RS or 1 IO, Address/Data – Input Address/Data – Output A0) LVCMOS H = Data H = Data L = Address (Command) L = Address (Command) D[15:0] 16 IO, Data Bus – Inputs/Outputs Data Bus – Outputs/Inputs LVCMOS INTR 1 O or I, INTR is asserted when the read data is ready Clock Disable - CLKDIS*: or LVCMOS and de-asserted upon a second CPU Read H = CLK output ON CLKDIS* cycle. L = CLK output LOW, allows for the Slave clock output to be held static if not used. CLK 1 IO, Clock Input Clock Output (Frequency Reference) – no LVCMOS phase relationship to data – frequency reference only. Mode 1 I, Mode Input Pin Mode Input Pin LVCMOS H = i80 Mode, H = i80 Mode, L = m68 Mode L = m68 Mode PLL_CON 3 I, PLL Configuration Input Pins – see Table 12 Clock Divisor Configuration Input Pins – see [2:0] LVCMOS Table 12 POWER/GROUND PINS VDDA 1 Power Power Supply Pin for the MPL Interface. 2.9V to 3.3V VSSA 1 Ground Ground Pin for the MPL Interface, a low impedance ground path is required between the Master and the Slave device - see Applications Information section. VDDcore 1 Power Power Supply Pin for the digital core. 2.9V to 3.3V VSScore 1 Ground Ground Pin for the digital core. VDDIO 2 Power Power Supply Pin for the parallel interface. 1.7V to 3.3V VSSIO 2 Ground Ground Pin for the parallel interface. 9 NC Not Connected (C3-5, D3-5, E3-5). NFBGA Package only. 1 Ground DAP = Ground. WQFN Package only. Table 3. Master Pinout - NFBGA Package MST 1 2 3 4 5 6 7 A D0 D1 D2 VDDA INTR MD1 MC B D3 D4 D5 VSSA M/S* Mode MD0 C D6 D7 NC NC NC CS2* MF1 D VDDIO VSSIO NC NC NC VSScore VDDcore E D8 D9 NC NC NC CS1* PLLCON2 F D10 D11 D12 VSSIO MF0 PLLCON1 PD* G D13 D14 D15 VDDIO A/D PLLCON0 CLK Table 4. Slave Pinout - NFBGA Package SLV 1 2 3 4 5 6 7 A D0 D1 D2 VDDA CLKDIS* MD0 MC B D3 D4 D5 VSSA M/S* Mode MD1 C D6 D7 NC NC NC CS2* MF1 D VDDIO VSSIO NC NC NC VSScore VDDcore E D8 D9 NC NC NC CS1* PLLCON2 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM2502 |
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