Start

H

A/D

D0

D1

D2

D3

D4

D5

D6

D7

R/

W*

CS1

/2

D8

D9

D10

D11

D12

D13

D14

D15

Start

H

R/

W*

MC

MD1

MD0

LM2502

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SNLS176L – JANUARY 2004 – REVISED MAY 2013

Table 6. Modes

Mode

Description

0

m68 Interface

(E, R/W*), 16-bit support

1

i80 Interface

(WR*, RD*), 16-bit support

It is not required that both the Master and the Slave to be configured in the same mode. For example the Master

may be configured as an 80xx (i80) interface while the Slave is configured for an 68xx (m68) interface.

Control information is carried over both MD lines. MD0 carries the D0–7 data bits while MD1 the D8–15 data bits.

See Figure 8.

WRITE TRANSACTION

The WRITE transaction consists of two MC edges of control information followed by 8 MC edges of write data.

Since WRITE transactions transfer information on both edges of MC it takes 5 MC cycles to complete a write

transaction. The MD0 line carries the Start bit (High), the A/D (Address/Data) bit and then the data payload of 8

bits (D0–7). The MD1 line carries the R/W* bit (Read/Write*), the CS1/2 bit and then the data payload of 8 bits

(D8–15). The data payload is sent least significant bit (LSB) first. The CS1/2 bit denotes which Chipset pin was

active. CS1/2 = HIGH designates that CS1* is active (Low). CS1/2 = LOW designates that CS2* is active (Low).

CS1* and CS2* LOW is not allowed.

Figure 8. Dual MD Link WRITE Transaction

READ TRANSACTION

The READ transaction is variable in length. It consists of four sections.

In the first section the Master sends a READ_Command to the slave. This command is sent in a single MC cycle

(2 edges) and uses a similar format to the 1st cycle of the WRITE transaction. The MD0 line carries the Start bit

(High) and the A/D (Address/Data) bit. The MD1 line carries the R/W* bit (High for reads) and the CS1/2 bit.

In the second section (TA’) the MD lines are turned around, such that the Master becomes the receiver and

Slave becomes the transmitter. The Slave must drive the MD lines low by the 14th clock edge. It may then idle

the line at the Logic Low state or drive the line High to indicate that read data transmission is starting. This

ensures that the MD lines are a stable LOW state and that the Low-to-High transition of the “Start” bit is seen by

the Master.

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