MC

MD0

MD1

MC

MD0

MD1

MC

MD0

Master

Slave

LM2502

LM2502

MD1

GND

LM2502

SNLS176L – JANUARY 2004 – REVISED MAY 2013

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FUNCTIONAL DESCRIPTION

BUS OVERVIEW

The LM2502 is a dual link Transceiver configurable part that supports a 16-bit CPU (m68 or i80) style interface.

The MPL physical layer is purpose-built for an extremely low power and low EMI data transmission while

requiring the fewest number of signal lines. No external line components are required, as termination is provided

internal to the MPL receiver. A maximum raw throughput of 307 Mbps (raw) is possible with this chipset. When

the protocol overhead is taken into account, a maximum data throughput of 245 Mbps is possible. The MPL

interface is designed for use with common 50

Ω to 100Ω lines using standard materials and connectors. Lines

may be microstrip or stripline construction. Total length of the interconnect is expected to be less than 20cm.

Figure 3. MPL Point-to-Point Bus

SERIAL BUS TIMING

Data valid is relative to both edges for a WRITE as shown in Figure 4. Data valid is specified as: Data Valid

before Clock, Data Valid after Clock, and Skew between data lines should be less than 500ps.

Figure 4. Dual Link Timing (WRITE)

Figure 5. Dual Link Timing (READ)

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Product Folder Links: LM2502