Primary

Display

(A)

Sub

Display

(B)

D[15:0]

A/D

CS1*

E (RD*)

R/W*(WR*)

MC

MD0

LM2502 MPL Slave

D[15:0]

A/D

CLK (optional)

E (RD*)

R/W*

CS1*

CS2*

BBP

or

APP

Processor

CLK

M/S*

PD*

M/S*

GND

PD*

LM2502 MPL Master

MD1

PLL_Con[2:0]

CS2*

INTR

R/W*(WR*)

Mode

Mode

PLL_Con

[2:0]

CLKDIS*

M/S* = H

PLL_CON[2:0],

Mode are application

dependent

GND

M/S* = L

PLL_CON[2:0], Mode, CLKDIS* are application

dependent, PD* = GPIO

LM2502

www.ti.com

SNLS176L – JANUARY 2004 – REVISED MAY 2013

Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer

Check for Samples: LM2502

1

FEATURES

DESCRIPTION

The LM2502 device is a dual link display interface

2

•

>300 Mbps Dual Link Raw Throughput

SERDES that adapts existing CPU / video busses to

•

MPL Physical Layer (MPL-0)

a low power current-mode serial MPL link. The

•

Pin Selectable Master / Slave Mode

chipset may also be used for a RGB565 application

with glue logic. The interconnect is reduced from 22

•

Frequency Reference Transport

signals to only 3 active signals with the LM2502

•

Complete LVCMOS / MPL Translation

chipset easing flex interconnect design, size and cost.

•

Interface Modes:

The Master Serializer (SER) resides beside an

–

16-bit CPU, i80 or m68 Style

application processor or baseband processor and

–

RGB565 with Glue Logic

translates a parallel bus from LVCMOS levels to

serial MPL levels for transmission over a flex cable

•

−30°C to 85°C Operating Range

and PCB traces to the Slave Deserializer (DES)

•

located near the display module.

•

Dual Display Support (CS1* & CS2*)

Dual display support is provided for a primary and

•

Via-less MPL Interconnect Feature

sub display through the use of two ChipSelect

•

signals. A Mode pin selects either a i80 or m68 style

interface.

•

The Power_Down (PD*) input controls the power

SYSTEM BENEFITS

state of the MPL interface. When PD* is asserted, the

MD1/0 and MC signals are powered down to save

•

Small Interface

current.

•

Low Power

The LM2502 implements the physical layer of the

•

Low EMI

MPL Standard (MPL-0). The LM2502 is offered in

•

Frequency Reference Transport

NOPB (Lead-free) NFBGA and WQFN packages.

•

Intrinsic Level Translation

Typical Application Diagram

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2004–2013, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.