GXM datasheet(45/244 Pages) NSC

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Processor Programming (Continued)

3.3.2.1

Control Registers

A map of the Control Registers (CR0, CR2, CR3, and

CR4) is shown in Table 3-6 and the bit definitions are given

in Table 3-7. (These registers should not be confused with

the CRRn registers.) The CR0 register contains system

control bits which configure operating modes and indicate

the general state of the CPU. The lower 16 bits of CR0 are

referred to as the Machine Status Word (MSW).

When operating in real mode, any program can read and

write the control registers. In protected mode, however,

only privilege level 0 (most-privileged) programs can read

and write these registers.

Table 3-6. Control Registers Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

8765

43210

CR4 Register

Control Register 4 (R/W)

RSVD

CR3 Register

Control Register 3 (R/W)

PDBR (Page Directory Base Register)

RSVD

CR2 Register

Control Register 2 (R/W)

PFLA (Page Fault Linear Address)

CR1 Register

Control Register 1 (R/W)

RSVD

CR0 Register

Control Register 0 (R/W)

RSVD

Machine Status Word (MSW)

Table 3-7. CR4-CR0 Bit Definitions

Bit

Name

Description

CR4 Register

Control Register 4 (R/W)

31:3

RSVD

Reserved: Set to 0 (always returns 0 when read).

2TSC

Time Stamp Counter Instruction:

If = 1 RDTSC instruction enabled for CPL = 0 only; reset state.

If = 0 RDTSC instruction enabled for all CPL states.

1:0

RSVD

Reserved: Set to 0 (always returns 0 when read).

CR3 Register

Control Register 3 (R/W)

31:12

PDBR

Page Directory Base Register: Identifies page directory base address on a 4 KB page boundary.

11:0

RSVD

Reserved: Set to 0.

CR2 Register

Control Register 2 (R/W)

31:0

PFLA

Page Fault Linear Address: With paging enabled and after a page fault, PFLA contains the linear address of the

address that caused the page fault.

CR1 Register

Control Register 1 (R/W)

31:0

RSVD

Reserved

CR0 Register

Control Register 0 (R/W)

Paging Enable Bit: If PG = 1 and protected mode is enabled (PE = 1), paging is enabled. After changing the

state of PG, software must execute an unconditional branch instruction (e.g., JMP, CALL) to have the change

take effect.

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