GXM datasheet(61/244 Pages) NSC

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Processor Programming (Continued)

3.5

OFFSET, SEGMENT, AND PAGING MECHANISMS

The mapping of address space into a sequence of mem-

ory locations (often cached) is performed by the offset,

segment and paging mechanisms.

In general, the offset, segment and paging mechanisms

work in tandem as shown below:

instruction offset

offset mechanism offset address

offset address

segment mechanism linear address

linear address

paging mechanism physical page.

As will be explained, the actual operations depend on sev-

eral factors such as the current operating mode and if

paging is enabled. Note: the paging mechanism uses part

of the linear address as an offset on the physical page.

3.6

OFFSET MECHANISM

In all operating modes, the offset mechanism computes

an offset (effective) address by adding together up to

three values: a base, an index and a displacement. The

base, if present, is the value in one of eight general regis-

ters at the time of the execution of the instruction. The

index, like the base, is a value that is contained in one of

the general registers (except the ESP register) when the

instruction is executed. The index differs from the base in

that the index is first multiplied by a scale factor of 1, 2, 4

or 8 before the summation is made. The third component

added to the memory address calculation is the displace-

ment that is a value supplied as part of the instruction.

Figure 3-3 illustrates the calculation of the offset address.

Nine valid combinations of the base, index, scale factor

and displacement can be used with the CPU instruction

set. These combinations are listed in Table 3-19 on page

61. The base and index both refer to contents of a register

as indicated by [Base] and [Index].

In real mode operation, the CPU only addresses the low-

est 1 MB of memory and the offset contains 16-bits. In

protective mode the offset contains 32 bits. Initialization

and transition to protective mode is described in Section

3.13.4 “Initialization and Transition to Protected Mode” on

page 87.

Figure 3-3. Offset Address Calculation

Table 3-19. Memory Addressing Modes

Index

Base

Displacement

Scaling

x1, x2, x4, x8

Offset Address

(Effective Address)

Addressing Mode

Base

Index

Scale

Factor

(SF)

Displacement

(DP)

Offset Address (OA)

Calculation

Direct

OA = DP

OA = [BASE]

Based

OA = [BASE] + DP

Index

OA = [INDEX] + DP

Scaled Index

OA = ([INDEX] * SF) + DP

Based Index

OA = [BASE] + [INDEX]

Based Scaled Index

OA = [BASE] + ([INDEX] * SF)

Based Index with

Displacement

OA = [BASE] + [INDEX] + DP

Based Scaled Index with

Displacement

OA = [BASE] + ([INDEX] * SF) + DP

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