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Revision 3.1

Integrated Functions (Continued)

4.2

INTERNAL BUS INTERFACE UNIT

The Geode GXm processor’s internal bus interface unit

provides control and interface functions to the internal C-

Bus (processor core, FPU, graphics pipeline, and L1

cache) and X-Bus (PCI controller, display controller, mem-

ory controller, and graphics accelerator) paths, provides

control for several sections of memory, and plays an

important part in the virtual VGA function.

The internal bus interface unit performs, without loss of

compatibility, the functions that previously required the

external pins IGNNE# and A20M#.

The internal bus interface unit provides configuration con-

trol for upto20different regionswithinsystemmemory. It

provides 19 configurable memory regions in the address

space between 640 KB and 1 MB, with separate control

for read access, write access, cacheability, and PCI

access.

The memory configuration control includes a top-of-mem-

ory register and hardware support for VGA emulation

plus, the capability to program 20 regions of the memory

map for different ROM configurations, and to locate mem-

ory-mapped I/O.

4.2.1

FPU Error Support

The FERR# (floating point error) and IGNNE# (ignore

numeric error) pins of the 486 microprocessor have been

replaced with an IRQ13 (interrupt request 13) pin. In DOS

systems, FPU errors are reported by the external vector

13. This mode of operation is specified by clearing the NE

bit (bit 5) in the CR0 register. If the NE bit is active, the

IRQ13 output of the GXm processor is always driven inac-

tive. If the NE bit is cleared, the GXm processor drives

IRQ13activewhenthe ES bit(bit7) inthe FPU Status

rupt with an OUT instruction of an 8-bit operand to F0h or

F1h. When the OUT cycle occurs, the IRQ13 pin is driven

inactive and the FPU starts ignoring numeric errors. When

the ES bit is cleared, the FPU resumes monitoring

numeric errors.

4.2.2

A20M Support

The GXm processor provides an A20M bit in the

BC_XMAP_1 Register (GX_BASE+ 8004h[21]) to replace

the A20M# pin on the 486 microprocessor. When the

A20M bit is set high, all non-SMI accesses will have

address bit 20 forced to zero. External hardware must do

an SMI trap on I/O locations that toggle the A20M# pin.

The SMI software can then change the A20M bit as

desired.

This maintains compatibility with software that depends

on wrapping the address at bit 20.

4.2.3

SMI Generation

The internal bus interface unit can generate SMI inter-

rupts whenever an I/O cycle in the VGA address range is

3B0h-3BFh and 3C0h-3CFh. An I/O cycle to 3D0h-3DFh

can be trapped. In case an external VGA card is present,

the Internal Bus Interface Unit default values will not gen-

erate an interrupt on VGA accesses. (Refer to Section

5.2.3.1 “SMI Generation” on page 168 for instructions on

how to configure the registers to generate the SMI inter-

rupt.)

4.2.4

640 KB to 1 MB Region

There are 19 configurable memory regions located

between 640KBand1MB. Threeofthe regionsare

A0000h-AFFFFh,

B0000h-B7FFFh,

and

B8000h-

BFFFFh. The area between C0000h and FFFFFh is

divided into 16 KB segments to form the remaining 16

regions. Each of these regions has four control bits to

allow any combination of read-access, write-access,

cache, and PCI-access capabilities (Table 4-11 on page

102).

In addition, each of the three regions defined in the

A0000h-BFFFh area of memory has a VGA control bit that

can cause the graphics pipeline to handle accesses to

that section of memory (see Table 5-3 on page 170).

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