GXM datasheet(84/244 Pages) NSC

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Revision 3.1

Processor Programming (Continued)

that no internal SMIs are generated in SMM, so the pro-

cessor ignores such events. If the internal and external

SMI signals are received simultaneously, then the internal

SMI is given priority to avoid losing the event.

The state diagram of the SMI_NEST and Nested SMI Sta-

tusbits are shown inFigure3-11witheachstate

explained next.

A. When the processor is outside of SMM, Nested SMI

Status is always clear and SMI_NEST is set high.

B. The first-level SMI interrupt is received by the

processor. The microcode clears SMI_NEST, sets

Nested SMI Status high and saves the previous

value of Nested SMI Status (0) in the SMI header.

C. The first-level SMI handler saves the header and

sets SMI_NEST high to re-enable SMI interrupts

from SMM.

D. A second-level (nested) SMI interrupt is received by

the processor. This SMI is taken even though the

processor is in SMM because the SMI_NEST bit is

set high. The microcode clears SMI_NEST, sets

Nested SMI Status high and saves the previous

value of Nested SMI Status (1) in the SMI header.

E. The second-level SMI handler saves the header and

sets SMI_NEST to re-enable SMI interrupts within

SMM. Another level of nesting could occur during

this period.

F. The second-level SMI handler clears SMI_NEST to

disable SMI interrupts, then restores its SMI header.

G. The second-level SMI handler executes an RSM.

The microcode sets SMI_NEST, and restores the

Nested SMI Status (1) based on the SMI header.

H. The first-level SMI handler clears SMI_NEST to

disable SMI interrupts, then restores its SMI header.

I. The first-level SMI handler executes an RSM. The

microcode sets SMI_NEST high and restores the

Nested SMI Status (0) based on the SMI header.

When the processor is outside of SMM, Nested SMI Sta-

tus is always clear and SMI_NEST is set high.

Figure 3-11. SMI Nesting State Machine

SMI_NEST

Nested SMI Status

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