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WM8753LEB/V データシート(PDF) 72 Page - Wolfson Microelectronics plc |
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WM8753LEB/V データシート(HTML) 72 Page - Wolfson Microelectronics plc |
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72 / 87 page  Advanced Information WM8753L w AI Rev 3.1 June 2004 72 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R18 (12h) Additional Control 7:6 VSEL [1:0] 11 Analogue Bias optimization 00: Lowest bias current, optimized for AVDD=1.8V 01: Low bias current, optimized for AVDD=2.5V 1X: Default bias current, optimized for AVDD=3.3V SAVING POWER BY REDUCING OVERSAMPLING RATE The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under the control of ADCOSR and DACOSR the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device. ADC 64x mode is not available in USB mode (USB = 1). In USB mode ADCOSR must be set to ‘0’. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 2 VXDACOSR 1 Voice DAC oversample rate select 1 = 64x (lowest power) 0 = 128x (best SNR) 1 ADCOSR 1 ADC oversample rate select 1 = 64x (lowest power) 0 = 128x (best SNR) R7 (07h) Sample Rate Control (2) 0 DACOSR 1 DAC oversample rate select 1 = 64x (lowest power) 0 = 128x (best SNR) Table 70 ADC and DAC Oversampling Rate Selection SAVING POWER BY REDUCING BIAS CURRENTS There are various biasing options within the WM8753L for increasing or reducing the bias current that is used by sections of the chip. The control of these is via the register bits MBIASBOOST, VDACBIASX0P5, MICBIASBST, BUFBIAS, IPBIASX0P5, ADCBIAS, OPBIASX0P5 and DMBIASX0P5 as shown in Figure 27. The performance of the chip may vary when the bias currents are changed from the default. masterbias micpreamp micpreamp local biasgen adc pga & zc adc pga & zc adc mixinv adc mixinv line mix rx mix mic detect alc mix local biasgen mixl mixr mixm dacinv dacinv dac dac voice dac dacinv rec mix local biasgen spkr pga & zc spkr pga & zc hp pga & zc hp pga & zc mono pga & zc out3 out4 mono 2 clkdet clkdet s/h buffer adc s/h buffer adc BUFBIAS[1:0] 00=x1 01=x0.25 10=x0.5 11=x1.5 OPBIASX0P5 0=x1 1=x0.5 DMBIASX0P5 0=x1 1=x0.5 IPBIASX0P5 0=x1 1=x0.5 MBIASBOOST 0=x1 1=x1.5 MICBIASBST[1:0] 00=x1 01=x2 10=x3 11=x4 2 2 ADCBIAS[1:0] 00=x1 01=x0.25 10=x0.5 11=x1.5 2 VDACBIASX0P5 0=x1 1=x0.5 Figure 27 Bias Current Control |
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