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WM8753LEB/V データシート(PDF) 33 Page - Wolfson Microelectronics plc |
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WM8753LEB/V データシート(HTML) 33 Page - Wolfson Microelectronics plc |
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33 / 87 page  WM8753L Advanced Information w AI Rev 3.1 June 2004 33 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 8:7 ALCSEL [1:0] 00 (OFF) ALC function select 00 = ALC off (PGA gain set by register) 01 = Right channel only 10 = Left channel only 11 = Stereo (PGA registers unused) 6:4 MAXGAIN [2:0] 111 (+30dB) Set Maximum Gain of PGA 111 : +30dB 110 : +24dB ….(-6dB steps) 001 : -6dB 000 : -12dB R12 (0Ch) ALC Control 1 3:0 ALCL [3:0] 1011 (-12dB) ALC target – sets signal level at ADC input 0000 = -28.5dB FS 0001 = -27.0dB FS … (1.5dB steps) 1110 = -7.5dB FS 1111 = -6dB FS 8 ALCZC 0 (zero cross off) ALC uses zero cross detection circuit. 7:4 ALCSR[3:0] 0000 ALC sample rate control (only used when in PCM mode, otherwise SR[4:0] bits control the sample rate) R13 (0Dh) ALC Control 2 3:0 HLD [3:0] 0000 (0ms) ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms … (time doubles with every step) 1111 = 43.691s 7:4 DCY [3:0] 0011 (192ms) ALC decay (gain ramp-up) time 0000 = 24ms 0001 = 48ms 0010 = 96ms … (time doubles with every step) 1010 or higher = 24.58s R14 (0Eh) ALC Control 3 3:0 ATK [3:0] 0010 (24ms) ALC attack (gain ramp-down) time 0000 = 6ms 0001 = 12ms 0010 = 24ms … (time doubles with every step) 1010 or higher = 6.14s Table 21 ALC Control |
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